# US 10,310,995 B1 · Arbitration control system and method for storage systems

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- Number: US 10,310,995 B1
- Document ID: US10310995B1
- Status: Granted
- Kind: B1
- Application number: 16/051,950
- Filed: 2018-08-01
- Granted: 2019-06-04
- Earliest claimed: 2018-08-01
- Assignees: Yadro International Ltd.
- Applicants: Yadro International Ltd
- Inventors: Mikhail Malygin; Maxim Trusov; Nikita Gutsalov; Ivan Andreyev; Ivan Tchoub; Alexey Sigaev; Artem Ikoev
- Web page: https://patentgrep.com/patent/US10310995B1

## CPC

- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 1/263: {Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence)}
- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- G06F 11/1441: {Resetting or repowering}
- G06F 11/2015: {Redundant power supplies (power supply failure G06F1/30)}
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0844: Multiple simultaneous or quasi-simultaneous cache accessing
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 13/362: with centralised access control
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G11C 5/141: {Battery and back-up supplies}
- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 2212/1048: Scalability
- G06F 2212/154: Networked environment
- G06F 2212/214: Solid state disk
- G06F 2212/2228: Battery-backed RAM
- G06F 2212/286: Mirrored cache memory
- G06F 2212/313: In storage device
- G06F 2212/401: Compressed data
- G06F 2212/402: Encrypted data
- G06F 2213/0026: PCI express
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells
- G11C 16/30: Power supply circuits
- G11C 2207/2245: Memory devices with an internal cache buffer
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A data storage system, including a host server having storage processors, a PCIe fabric, and a GBE fabric, and two or more data storage modules having a bank of DRAM, long-term storage drives, a host interface, including a PCIe interface and a GBE interface, an application specific integrated circuit connected to the host interface, the storage drives, and the DRAM, and a battery, the battery providing power to the DRAM and SSDs in an event of failure of a main power supply. Data streams transmitted from the host server via a PCIe connection of the PCIe fabric are received at the host interface and placed directly in DRAM as a write-back cache operation. In addition, the battery provides the DRAM with non-volatile memory capabilities and the storage modules with portability. A method for arbitration of write requests between the storage processors of the data storage system is also disclosed.

## Claims

### Claim 1

A data storage module, comprising:
a bank of dynamic random access memory (DRAM);
a host interface, including a Peripheral Component Interconnect Express (PCIe) interface;
an application specific integrated circuit (ASIC) connected to the host interface and the DRAM; and
a battery, the battery providing power to the DRAM and SSDs in an event of failure of a main power supply,
wherein the ASIC provides the DRAM as write-back cache via the PCIe interface to storage processors, the storage processors accessing the data module as extensions of local memory address space of the storage processors,
wherein the power provided by the battery and the main power supply makes the DRAM non-volatile, and
wherein the ASIC arbitrates write requests received at the storage processors, the storage processors fetching write request data from the DRAM for final placement.

### Claim 2 (depends on 1)

The data storage module of claim 1, wherein the ASIC receives write data associated with a write request from a host application, via the PCIe interface and the storage processors, and sequentially hashes the data stream during receipt so that, upon completion of the receipt of the write data, the ASIC can confirm accurate receipt of the write data.

### Claim 3 (depends on 2)

The data storage module of claim 2, wherein after receipt of the write data and the write request, the data storage module provides the write data to storage processors until final placement of the write data.

### Claim 4 (depends on 1)

The data storage module of claim 1, wherein the ASIC comprises: a cache, a memory controller, a power manager, and a CPU.

### Claim 5 (depends on 1)

The data storage module of claim 1, wherein the data storage module is connected to at least two additional data storage modules via a PCIe fabric and a GBE fabric.

### Claim 6 (depends on 5)

The data storage module of claim 5, wherein the data storage module and at least two additional data storage modules provide active-active control for the storage processors and arbitrate read and write requests sent to the storage processors by a host application.

### Claim 7 (depends on 1)

The data storage module of claim 1, wherein the ASIC executes applications, encrypts data, compiles applications, compresses data, hashes data in real time, and conducts data analysis such as sorting, comparing, merging, and searches as internal processes.

### Claim 8 (depends on 1)

A distributed active-active controller for the storage processors, comprising at least two data storage modules according to claim 1, wherein the at least two data storage modules are connected via a PCIe fabric and a GBE fabric,
wherein the active-active controller provides directly accessible cache to central processing units (CPUs) of the storage processors,
wherein the active-active controller receives write requests and corresponding data for temporary placement into DRAM from the storage processors,
wherein the active-active controller arbitrates the write requests in DRAM for all storage processors until final placement into final media of a storage system, and
wherein the active-active controller arbitrates read requests corresponding to data in DRAM to de-conflict read and write requests from a host application.

### Claim 9 (depends on 8)

The distributed active-active controller of claim 8, wherein atomicity of operations is maintained by the arbitration of write requests by the active-active controller.

### Claim 10 (depends on 1)

The data storage module of claim 1, wherein the DRAM is directly accessible by central processing units (CPUs) of the storage processors.

### Claim 11 (depends on 1)

The data storage module of claim 1, further comprising: a NVMe adaptor connecting NAND flash memory to the ASIC.

### Claim 12 (depends on 1)

The data storage module of claim 1, wherein the data storage module is portable, swappable, and retains data stored in the DRAM while being swapped or transported.

### Claim 13 (depends on 1)

The data storage module of claim 1, wherein all the storage processors fetch the write request data from the DRAM and process the write requests locally, the data storage module storing the write request data until the final placement, any of the storage processors being able to respond to a read request for the write request data.

### Claim 14

A data storage system, comprising:
a host server, comprising: storage processors, a PCIe fabric, and a GBE fabric;
at least two data storage modules, each comprising:
a bank of dynamic random access memory (DRAM);
NAND flash memory;
a host interface, including a Peripheral Component Interconnect Express (PCIe) interface and a gigabyte Ethernet (GBE) interface;
an application specific integrated circuit (ASIC) connected to the host interface and the DRAM; and
a battery, the battery providing power to the DRAM and NAND flash memory in an event of failure of a main power supply,
wherein write requests and write data forwarded by the host server, via a PCIe connection of the PCIe fabric, from a host application is received at the host interface and placed directly in DRAM as a write-back cache or a write-ahead log, and
wherein the write requests in DRAM are arbitrated between storage processors for processing the write requests by the ASIC.

### Claim 15

A method for arbitration of write requests between storage processors of a storage system, comprising:
providing a smart non-volatile random access memory (NVRAM) module including a bank of dynamic random access memory (DRAM) and a host interface both connected to an application specific integrated circuit (ASIC), and a battery for powering the DRAM;
upon receiving a write request with write data from a host application at the storage processors, forwarding the write request and the write data to the smart NVRAM module, the smart NVRAM module automatically acknowledging receipt to the storage processors, and the storage processors forwarding the receipt to the host application;
storing the write request and write data in the DRAM of the smart NVRAM module, and notifying the storage processors of an address of the write request and the write data, wherein central processing units (CPUs) of the storage processors can access the DRAM as additional memory address space;
fetching the write request and write data, by a specific storage processor of the storage processors, for final placement in a long-term storage media,
wherein, before final placement, if the storage processors receive a read request for the write data, the smart NVRAM module de-conflicts the read request and the write request and serves the write data up to the host application via the storage processors.