# US 10,310,988 B2 · Address translation for sending real address to memory subsystem in effective address based load-store unit

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- Number: US 10,310,988 B2
- Document ID: US10310988B2
- Status: Granted
- Kind: B2
- Application number: 15/726,650
- Filed: 2017-10-06
- Published: 2019-04-11
- Granted: 2019-06-04
- Earliest claimed: 2017-10-06
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bryan Lloyd; Balaram Sinharoy; Shih-Hsiung S. Tung
- Web page: https://patentgrep.com/patent/US10310988B2

## CPC

- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/3824: {Operand accessing}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/384: {Register renaming}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 2212/65: Details of virtual memory and virtual address translation
- G06F 2212/651: Multi-level translation tables
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Technical solutions are described for executing one or more out-of-order instructions by a processing unit. An example method includes executing, by a load-store unit (LSU), instructions from an out-of-order (OoO) window. The OoO execution includes determining an effective address being used by a load instruction from the OoO window. Further, the execution includes determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT). In response to the effective address being present in the EAD, the execution includes accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address, and issuing the load instruction using the real address from the corresponding ERT entry.

## Claims

### Claim 1

A processing unit for executing one or more instructions, the processing unit comprising:
a load-store unit (LSU) for transferring data between memory and registers, the load-store unit configured to execute a plurality of instructions in an out-of-order (OoO) window, the execution comprises:
determining an effective address being used by a load instruction from the OoO window;
determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT); and
in response to the effective address being present in the EAD:
accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address; and
issuing the load instruction using the real address from the corresponding ERT entry.

### Claim 2 (depends on 1)

The processing unit of claim 1, wherein executing the load instruction from the plurality of instructions in the OoO window further comprises:
in response to the effective address being absent in the EAD:
determining presence of the effective address in the ERT, and in response to the effective address being present in the ERT:
accessing an ERT entry that includes the effective address, the ERT entry including the real address for the effective address; and
issuing the load instruction using the real address from the ERT entry.

### Claim 3 (depends on 2)

The processing unit of claim 2, wherein determining presence of the effective address in the ERT is based in comparing the effective address and a thread identifier associated with a LSU thread executing the load instruction with a plurality of ERT entries.

### Claim 4 (depends on 2)

The processing unit of claim 2, wherein the ERT entry is a first ERT entry, and executing the load instruction from the plurality of instructions in the OoO window further comprises:
in response to the effective address being absent in the ERT:
determining the real address for the effective address using a content addressable memory (CAM) port; and
adding a second ERT entry to include a mapping between the effective address and the real address obtained using the CAM port.

### Claim 5 (depends on 4)

The processing unit of claim 4, wherein the second ERT entry is added in place of a least recently used ERT entry.

### Claim 6 (depends on 4)

The processing unit of claim 4, wherein the EAD entry is a first EAD entry, and further, in response to the effective address being absent in the ERT, adding a second EAD entry to include a mapping between the effective address and an index of the second ERT entry.

### Claim 7 (depends on 1)

The processing unit of claim 1, wherein the ERT comprises a number of partitions, one partition for each load instruction issued concurrently by the LSU.

### Claim 8

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
issuing, by a load-store unit (LSU), a plurality of instructions from an out-of-order (OoO) window, the issuing comprising:
determining an effective address being used by a load instruction from the OoO window;
determining presence of the effective address in an effective address directory (EAD) by identifying an EAD entry in the EAD, the EAD entry maps the effective address with an index of a corresponding effective-real table (ERT) entry from an effective-real table (ERT); and
in response to the effective address being present in the EAD:
accessing the corresponding ERT entry of the effective address of the load instruction, the corresponding ERT entry including a real address for the effective address; and
issuing the load instruction using the real address from the corresponding ERT entry.

### Claim 9 (depends on 8)

The computer program product of claim 8, wherein executing the load instruction from the plurality of instructions in the OoO window further comprises:
in response to the effective address being absent in the EAD:
determining presence of the effective address in the ERT, and in response to the effective address being present in the ERT:
accessing an ERT entry that includes the effective address, the ERT entry including the real address for the effective address; and
issuing the load instruction using the real address from the ERT entry.

### Claim 10 (depends on 9)

The computer program product of claim 9, wherein determining presence of the effective address in the ERT is based in comparing the effective address and a thread identifier associated with a LSU thread executing the load instruction with a plurality of ERT entries.

### Claim 11 (depends on 9)

The computer program product of claim 9, wherein the ERT entry is a first ERT entry and executing the load instruction from the plurality of instructions in the OoO window further comprises:
in response to the effective address being absent in the ERT:
determining the real address for the effective address using a content addressable memory (CAM) port; and
adding a second ERT entry to include a mapping between the effective address and the real address obtained using the CAM port.

### Claim 12 (depends on 11)

The computer program product of claim 11, wherein the EAD entry is a first EAD entry, and further, in response to the effective address being absent in the ERT, adding a second EAD entry to include a mapping between the effective address and an index of the second ERT entry.

### Claim 13 (depends on 8)

The computer program product of claim 8, wherein the ERT comprises a number of partitions, one partition for each load instruction issued concurrently by the LSU.