# US 10,310,987 B2 · Systems and methods for accessing a unified translation lookaside buffer

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- Number: US 10,310,987 B2
- Document ID: US10310987B2
- Status: Granted
- Kind: B2
- Application number: 15/678,057
- Filed: 2017-08-15
- Published: 2018-01-25
- Granted: 2019-06-04
- Earliest claimed: 2012-03-07
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Karthikeyan Avudaiyappan; Mohammad Abdallah
- Web page: https://patentgrep.com/patent/US10310987B2

## CPC

- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/1054: {the data cache being concurrently physically addressed}
- G06F 12/1063: {the data cache being concurrently virtually addressed}
- G06F 2212/1016: Performance improvement
- G06F 2212/1021: Hit rate improvement
- G06F 2212/152: Virtualized environment, e.g. logically partitioned system
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/651: Multi-level translation tables
- G06F 2212/652: Page size control
- G06F 2212/657: Virtual address space management
- G06F 2212/681: Multi-level TLB, e.g. microTLB and main TLB
- G06F 2212/684: TLB miss handling
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

## Claims

### Claim 1

A method for accessing a unified translation lookaside buffer (TLB), comprising:
searching a page size cache mapping virtual addresses to page sizes for an input virtual address to identify a page size; and
looking up a physical address translation of the virtual address in a second level TLB using the page size.

### Claim 2 (depends on 1)

The method of claim 1, wherein searching the page size cache is in response to a miss of the virtual address in a level one TLB (L1TLB).

### Claim 3 (depends on 1)

The method of claim 1 wherein searching the page size cache and looking up the physical address is performed in a single clock cycle.

### Claim 4 (depends on 1)

The method of claim 1 wherein the page size determines bits of the virtual address that are translated to form the physical address.

### Claim 5 (depends on 1)

The method of claim 1 wherein the page size determines bits of the virtual address that are translated which identify an address where a desired translation table entry (TTE) is located.

### Claim 6 (depends on 1)

The method of claim 1 wherein a search of the second level TLB based on the page size is executed to find a physical address wherein said second level TLB is of n-way associativity.

### Claim 7 (depends on 1)

The method of claim 1 wherein the page size is a correct size of the page that is associated with the physical address.

### Claim 8 (depends on 1)

The method of claim 1 wherein the page size cache does not provide virtual address to physical address translation.

### Claim 9

A unified translation lookaside buffer (TLB), comprising:
a page size cache mapping virtual addresses to page size;
a second level TLB mapping virtual addresses and page sizes to physical addresses; and
a unified TLB access component to search the page size cache with an input virtual address to identify a page size, and to look up a physical address translation of the virtual address in the second level TLB using the page size.

### Claim 10 (depends on 9)

The unified TLB of claim 9, further comprising:
a level one TLB (L1TLB).

### Claim 11 (depends on 10)

The unified TLB of claim 10, wherein the unified TLB access component is further to search the page size cache in response to a miss of the input virtual address in the level one TLB (L1TLB).

### Claim 12 (depends on 9)

The unified TLB of claim 9, wherein unified TLB access component searches the page size cache and looks up the physical address in a single clock cycle.

### Claim 13 (depends on 9)

The unified TLB of claim 9, wherein the page size determines the bits of virtual address that are translated which identify an address where a desired translation table entry (TTE) is located.

### Claim 14 (depends on 9)

The unified TLB of claim 9 wherein the second level TLB is of n-way associativity.

### Claim 15 (depends on 9)

The unified TLB of claim 9 wherein the page size is a correct size of the page that is associated with the physical address.

### Claim 16

A computer system comprising:
a processor;
a memory;
a memory management unit (MMU) coupled to the processor and the memory, the MMU to access memory in response to requests from the processor; and
a unified translation lookaside buffer (TLB) to convert virtual addresses provided by the MMU into physical addresses in the memory, the unified TLB including a page size cache mapping virtual addresses to page size, a second level TLB mapping virtual addresses and page sizes to physical addresses, and a unified TLB access component to search the page size cache with an input virtual address to identify a page size, and to look up a physical address translation of the virtual address in the second level TLB using the page size.

### Claim 17 (depends on 16)

The computer system of claim 16, wherein the unified TLB further comprises:
a level one TLB (L1TLB).

### Claim 18 (depends on 17)

The computer system of claim 17, wherein the unified TLB access component is further to search the page size cache in response to a miss of the input virtual address in the level one TLB (L1TLB).

### Claim 19 (depends on 16)

The computer system of claim 16, wherein unified TLB access component searches the page size cache and looks up the physical address in a single clock cycle.

### Claim 20 (depends on 16)

The computer system of claim 16, wherein the page size determines bits of the virtual address that are translated which identify an address where a desired translation table entry (TTE) is located.