# US 10,310,978 B2 · Apparatus and method for multi-level cache request tracking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,978 B2 - Document ID: US10310978B2 - Status: Granted - Kind: B2 - Application number: 15/721,499 - Filed: 2017-09-29 - Published: 2019-04-04 - Granted: 2019-06-04 - Earliest claimed: 2017-09-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Robert G. Blankenship; Samantika S. Sury - Web page: https://patentgrep.com/patent/US10310978B2 ## CPC - G06F 12/0815: Cache consistency protocols - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 2212/1008: Correctness of operation, e.g. memory ordering - G06F 2212/452: Instruction code - G06F 2212/60: Details of cache memory - G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for multi-level cache request tracking. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; a memory subsystem comprising a system memory and a multi-level cache hierarchy; a primary tracker to store a first entry associated with a memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to a second cache; primary tracker allocation circuitry to allocate and deallocate entries within the primary tracker; a secondary tracker to store a second entry associated with the memory request; secondary tracker allocation circuitry to allocate and deallocate entries within the secondary tracker; the primary tracker allocation circuitry to deallocate the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved, the secondary tracker allocation circuitry to deallocate the second entry in response to a second indication related to transmission of the cache line to the second cache. ## Claims ### Claim 1 A processor comprising: one or more cores to execute instructions and process data; a memory subsystem comprising a system memory and a multi-level cache hierarchy; a primary tracker to store a first entry associated with a memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to a second cache; primary tracker allocation circuitry to allocate and deallocate entries within the primary tracker; a secondary tracker to store a second entry associated with the memory request; secondary tracker allocation circuitry to allocate and deallocate entries within the secondary tracker; the primary tracker allocation circuitry to deallocate the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved, the secondary tracker allocation circuitry to deallocate the second entry in response to a second indication related to transmission of the cache line to the second cache. ### Claim 2 (depends on 1) The processor of claim 1 wherein the second indication comprises an indication that the cache line has been successfully transmitted to the second cache. ### Claim 3 (depends on 1) The processor of claim 1 wherein the first indication that one or more cache coherence requirements associated with the cache line have been resolved comprises an indication that the cache line is coherent as determined by cache coherence circuitry of the processor. ### Claim 4 (depends on 1) The processor of claim 1 further comprising: a fill buffer into which the cache line is to be written by data distribution circuitry of the processor, the cache line to be transferred to the second cache after being written into the fill buffer. ### Claim 5 (depends on 4) The processor of claim 4 wherein the second cache comprises a mid-level cache (MLC). ### Claim 6 (depends on 1) The processor of claim 1 wherein the primary tracker comprises a content addressable memory (CAM). ### Claim 7 (depends on 1) The processor of claim 1 wherein the secondary tracker comprises a static random access memory (SRAM). ### Claim 8 (depends on 1) The processor of claim 1 wherein the primary tracker allocation circuitry is to allocate the first entry in response to detecting the memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to the second cache. ### Claim 9 (depends on 8) The processor of claim 8 wherein the first entry comprises a valid indication and a portion of an address associated with the memory request. ### Claim 10 (depends on 9) The processor of claim 9 wherein the second entry comprises data identifying a location within the second cache into which the cache line is to be copied. ### Claim 11 (depends on 1) The processor of claim 1 wherein the second entry is retained when the first entry has been deallocated. ### Claim 12 A method comprising: allocating a first entry in a primary tracker of a processor in response to a memory request to transfer a cache line from a system memory or a first cache within a cache hierarchy to a second cache; allocating a second entry in a secondary tracker of the processor, the second entry to be associated with the memory request; deallocating the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved; and deallocating the second entry in response to a second indication related to transmission of the cache line to the second cache. ### Claim 13 (depends on 12) The method of claim 12 wherein the second indication comprises an indication that the cache line has been successfully transmitted to the second cache. ### Claim 14 (depends on 12) The method of claim 12 wherein the first indication that one or more cache coherence requirements associated with the cache line have been resolved comprises an indication that the cache line is coherent as determined by cache coherence circuitry of the processor. ### Claim 15 (depends on 12) The method of claim 12 further comprising: writing the cache line to a fill buffer; and transferring the cache line to the second cache after being written into the fill buffer. ### Claim 16 (depends on 15) The method of claim 15 wherein the second cache comprises a mid-level cache (MLC). ### Claim 17 (depends on 12) The method of claim 12 wherein the primary tracker comprises a content addressable memory (CAM). ### Claim 18 (depends on 12) The method of claim 12 wherein the secondary tracker comprises a static random access memory (SRAM). ### Claim 19 (depends on 12) The method of claim 12 wherein the primary tracker allocation circuitry is to allocate the first entry in response to detecting the memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to the second cache. ### Claim 20 A non-transitory machine-readable medium having program code stored therein which, when executed by a machine, causes the machine to perform the operations of: allocating a first entry in a primary tracker of a processor in response to a memory request to transfer a cache line from a system memory or a first cache within a cache hierarchy to a second cache; allocating a second entry in a secondary tracker of the processor, the second entry to be associated with the memory request; deallocating the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved; and deallocating the second entry in response to a second indication related to transmission of the cache line to the second cache.