# US 10,310,976 B2 · System and method for concurrently checking availability of data in extending memories > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,976 B2 - Document ID: US10310976B2 - Status: Granted - Kind: B2 - Application number: 14/835,988 - Filed: 2015-08-26 - Published: 2015-12-17 - Granted: 2019-06-04 - Earliest claimed: 2007-03-15 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Shine Chung - Web page: https://patentgrep.com/patent/US10310976B2 ## CPC - G06F 12/0811: with multilevel cache hierarchies - G06F 3/0613: {in relation to throughput} - G06F 3/064: {Management of blocks} - G06F 3/0683: {Plurality of storage devices} - G06F 12/0846: Cache with multiple tag or data arrays being simultaneously accessible - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 2212/1016: Performance improvement - G06F 2212/1021: Hit rate improvement - G06F 2212/451: Stack data - H10W 90/00: Package configurations - H10W 90/752: {between stacked chips} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A memory system for use in a system-in-package device (SiP) is disclosed. The memory system includes two cache memories. The first cache memory is on a first die of the SiP and the second cache memory is on a second die of the SiP. Both cache memories include tag random access memories (RAMs) corresponding to data stored in the corresponding cache memories. The second cache memory is of a different cache level from the first cache memories. Also, the first cache memory is on a first die of the SiP, and the second cache memory includes a first portion on the first die of the SiP, and a second portion on a second die of the SiP. Both cache memories can be checked concurrently for data availability by a single physical address. ## Claims ### Claim 1 A system for use in a system-in-package device (SiP), the system comprising: a first cache memory of Level 1 on a first die of the SiP, the first cache memory implemented in a multiple-way set association and including a first tag random access memory (RAM) with a tag RAM array for each set, for storing one or more tags corresponding to data stored in the corresponding sets of the first cache memory; a second cache memory of a level different from Level 1, the second cache memory implemented in a multiple-way set association and including a first portion of the second cache memory on the first die of the SiP, and a second portion of the second cache memory on a second die of the SiP, the first portion of the second cache memory including a data RAM, the second cache memory including a second tag RAM with a tag RAM array for each set, for storing one or more tags corresponding to data stored in the corresponding sets of the second cache memory; a control logic circuit coupled to the first and second cache memories and configured to control a multiplexer for outputting data from either of the first and second cache memories; wherein the first and second cache memories are coupled to a single physical address, wherein the single physical address is divided into a first number of tag bits, a second number of index bits, and a third number of offset bits associated with the first tag RAM of the first cache memory; wherein the single physical address is divided into a fourth number of tag bits, a fifth number of index bits, and a sixth number of offset bits associated with the second tag RAM of the second cache memory, wherein one of a first ratio of the first number to the second number and a second ratio of the fourth number to the fifth number is greater than one, and the other of the first and second ratios is greater than two; and wherein the first number of tag bits and the second number of index bits of the single physical address provided to the first tag RAM of the first cache memory are different from the fourth number of tag bits and the fifth number of index bits provided to the second tag RAM of the second cache memory, such that both the first cache memory of Level 1and the second cache memory can be checked concurrently for data availability by the single physical address; and a processor coupled to the first cache memory and second cache memory and configured to: randomize a write-physical-address associated with data-to-store to generate a cache memory selection bit; select a write-cache-memory from the first and second cache memories based on the cache memory selection bit; and store the data-to-store at the write-physical-address in the write-cache-memory. ### Claim 2 (depends on 1) The system of claim 1, wherein the first cache memory is a 3-way set association cache memory. ### Claim 3 (depends on 1) The system of claim 1, wherein the tag RAM arrays for the first tag RAM are identical. ### Claim 4 (depends on 1) The system of claim 1, wherein the first die further includes a processor. ### Claim 5 (depends on 4) The system of claim 4, wherein the processor is a multi-core processor. ### Claim 6 (depends on 1) The system of claim 1, wherein the first number is different from the fourth number, and wherein the third number is the same as the sixth number. ### Claim 7 (depends on 1) The system of claim 1, wherein the second number is different from the fifth number. ### Claim 8 (depends on 1) The system of claim 1, wherein the second die is stacked on the first die. ### Claim 9 (depends on 1) The system of claim 1, wherein the first or second tag RAMs further comprises one or more attribute bits for memory coherent operations. ### Claim 10 A system for use in a system-in-package device (SiP), the system comprising: a first cache memory of Level 1 on a first die of the SiP, the first cache memory including a first tag random access memory (RAM) with multiple identical tag RAM arrays, for storing one or more tags corresponding to data stored in different sets of the first cache memory; a second cache memory of a level different from Level 1, the second cache memory including a first portion of the second cache memory on the first die of the SiP, and a second portion of the second cache memory on a second die of the SiP, the first portion of the second cache memory including a data RAM, the second cache memory including a second tag RAM with multiple identical tag RAM arrays for storing one or more tags corresponding to data stored in the different sets of the second cache memory; and a control logic circuit coupled to the first and second cache memories and configured to control a multiplexer for outputting data from either of the first and second cache memories; wherein the first and second cache memories are separate modules, but are coupled to a single physical address, wherein the single physical address is divided into a first number of tag bits, a second number of index bits, and a third number of offset bits associated with the first tag RAM of the first cache memory; wherein the single physical address is divided into a fourth number of tag bits, a fifth number of index bits, and a sixth number of offset bits associated with the second tag RAM of the second cache memory, wherein one of a first ratio of the first number to the second number and a second ratio of the fourth number to the fifth number is greater than one, and the other of the first and second ratios is greater than two, wherein the third number is equal to the sixth number, and wherein the first number of tag bits and the second number of index bits of the single physical address provided to the first tag RAM of the first cache memory are different from the fourth number of tag bits and the fifth number of index bits provided to the second tag RAM of the second cache memory, such that both the first cache memory of Level 1and the second cache memory can be checked concurrently for data availability by the single physical address; and a processor coupled to the first cache memory and second cache memory and configured to: randomize a write-physical-address associated with data-to-store to generate a cache memory selection bit; select a write-cache-memory from the first and second cache memories based on the cache memory selection bit; and store the data-to-store at the write-physical-address in the write-cache-memory. ### Claim 11 (depends on 10) The system of claim 10, wherein the first cache memory is a 3-way set association cache memory. ### Claim 12 (depends on 10) The system of claim 10, wherein the first die further includes the processor. ### Claim 13 (depends on 12) The system of claim 12, wherein the processor is a multi-core processor. ### Claim 14 (depends on 10) The system of claim 10, wherein the first number is different from the fourth number. ### Claim 15 (depends on 10) The system of claim 10, wherein the second number is different from the fifth number. ### Claim 16 (depends on 10) The system of claim 10, wherein the second die is stacked on the first die. ### Claim 17 (depends on 10) The system of claim 10, wherein the first or second tag RAMs further comprises one or more attribute bits for memory coherent operations. ### Claim 18 A system for use in a system-in-package device (SiP) including a dual-core processor, the system comprising: a first cache memory of Level 1 on a first die of the SiP, the first cache memory implemented in a multiple-way set association and including a first tag random access memory (RAM) with at least two identical tag RAM arrays, for storing one or more tags corresponding to data stored in different sets of the first cache memory; a second cache memory of a level different from Level 1, the second cache memory implemented in a multiple-way set association and including a first portion of the second cache memory on the first die of the SiP, and an extension portion of the second cache memory on a second die of the SiP, the first portion of the second cache memory including a data RAM, the second cache memory including a second tag RAM with at least two identical tag RAM arrays for storing one or more tags corresponding to data stored in the different sets of the second cache memory; a control logic circuit coupled to the first and second cache memories and configured to control a multiplexer for outputting data from either of the first and second cache memories; and wherein the first and second cache memories are coupled to a single physical address, wherein the second cache memory is a shared cache for the dual-core processor, wherein the single physical address is divided into a first number of tag bits, a second number of index bits, and a third number of offset bits associated with the first tag RAM of the first cache memory; wherein the single physical address is divided into a fourth number of tag bits, a fifth number of index bits, and a sixth number of offset bits associated with the second tag RAM of the second cache memory, wherein one of a first ratio of the first number to the second number and a second ratio of the fourth number to the fifth number is greater than one, and the other of the first and second ratios is greater than two, wherein the third number is equal to the sixth number, and wherein the first number of tag bits and second number of index bits of the physical address provided to the first tag RAM of the first cache memory are different from the fourth number of tag bits and fifth number of index bits provided to the second tag RAM of the second cache memory, such that both the first cache memory of Level 1and the second cache memory can be checked concurrently for data availability by the single physical address; wherein the processor is configured to: randomize a write-physical-address associated with data-to-store to generate a cache memory selection bit; and select a write-cache-memory from the first and second cache memories based on the cache memory selection bit for storing the data-to-store. ### Claim 19 (depends on 18) The system of claim 18, wherein the second die is stacked on the first die. ### Claim 20 (depends on 18) The system of claim 18, wherein the first cache memory is a 3-way set association cache memory.