# US 10,310,972 B1 · Memory apparatus and method of wear-leveling of a memory apparatus

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- Number: US 10,310,972 B1
- Document ID: US10310972B1
- Status: Granted
- Kind: B1
- Application number: 16/271,431
- Filed: 2019-02-08
- Published: 2019-06-06
- Granted: 2019-06-04
- Earliest claimed: 2017-03-10
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Donggun Kim; Yong Ju Kim; Do Sun Hong
- Web page: https://patentgrep.com/patent/US10310972B1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/1466: {Key-lock mechanism}
- G06F 2212/1052: Security improvement
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7211: Wear leveling
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

## Claims

### Claim 1

A method of wear-leveling of a memory apparatus, the method comprising:
allocating a plurality of storage blocks and a plurality of free blocks in a memory; and
performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks, a result of a logic operation of a logical page address of each of pages in the first storage block and a first security refresh key being remapped to a physical page address of each of pages in the first free block.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the storage blocks is allocated as a block in which data is stored, and each of the free blocks is allocated as an empty block in which no data is stored.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first security refresh key is randomly generated.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
performing a second global wear-leveling to move data of a second storage block, which is a cold block among the storage blocks, to the first storage block emptied by the first global wear-leveling, after performing the first global wear-leveling.

### Claim 5 (depends on 4)

The method of claim 4, wherein performing the second global wear-leveling includes remapping the result of the logic operation of a logical page address of each of pages in the second storage block and a second security refresh key to a physical page address of each of pages in the first free blocks.

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
switching the second storage block emptied by the second global wear-leveling to a free block.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
performing a local wear-leveling to move data in units of pages in any one of the storage blocks.

### Claim 8 (depends on 5)

The method of claim 5, wherein performing a local wear-leveling includes remapping a result of a logic operation of a logical page address of each of pages in the storage blocks and a third security refresh key to a physical page address of each of the pages in the storage blocks.

### Claim 9 (depends on 8)

The method of claim 8, wherein the third security refresh key is randomly generated.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
determining the hot block rather than a cold block if counter values associated with a current mapping address corresponding to a logical address requested to be written to exceed a preconfigured value.
