# US 10,310,947 B1 · Log-based rollback-recovery > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,947 B1 - Document ID: US10310947B1 - Status: Granted - Kind: B1 - Application number: 14/152,806 - Filed: 2014-01-10 - Granted: 2019-06-04 - Earliest claimed: 2006-01-18 - Assignees: Open Invention Network, LLC - Applicants: Open Invention Network LLC - Inventors: Srinidhi Varadarajan; Joseph F. Ruscio - Web page: https://patentgrep.com/patent/US10310947B1 ## CPC - G06F 11/1458: {Management of the backup or restore process} - G06F 11/1438: {Restarting or rejuvenating} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Log-Based Rollback Recovery for system failures. The system includes a storage medium, and a component configured to transition through a series of states. The component is further configured to record in the storage medium the state of the component every time the component communicates with another component in the system, the system being configured to recover the most recent state recorded in the storage medium following a failure of the component. ## Claims ### Claim 1 A system for improved recovery by avoiding replaying of non-deterministic events, comprising: a storage medium; a hardware component configured to perform a process resulting in a transition of the component through a series of states; a spare component capable of performing one or more operations of the hardware component; a recovery manager configured to respond to a failure of the component after the component has undergone at least one programmed and replayable non-deterministic event internal to a processing node of the component since a most recent state of the component being recorded in the storage medium, and before the non-deterministic event is communicated to other components external to the processing node, by recovering the most recent state of the component recorded in the storage medium, independent of an operating system, and loading the recovered state into the spare component without the at least one non-deterministic event internal to the processing node being replayed and communicated to other components external to the processing node, wherein after the loading, the spare component is configured to continue to perform the process based on the recovered state, wherein the at least one programmed and replayable non-deterministic event comprises a determination of an order in which at least two threads will have access to a state variable. ### Claim 2 (depends on 1) The system of claim 1 wherein the component is further configured to perform a process having multiple threads. ### Claim 3 (depends on 2) The system of claim 2 wherein at least two of the threads share a common state as the component transitions through the series of states. ### Claim 4 (depends on 3) The system of claim 3 wherein the common state comprises an access by said at least two of the threads to a common resource. ### Claim 5 (depends on 1) The system of claim 1 wherein the component is further configured to perform multiple processes in parallel, the processes resulting in the component that transitions through the series of states. ### Claim 6 (depends on 5) The system of claim 5 wherein at least one of the processes comprises multiple threads. ### Claim 7 (depends on 5) The system of claim 5 wherein at least two of the processes share a common state as the component transitions through the series of states. ### Claim 8 (depends on 7) The system of claim 7 wherein the common state comprises an access by said at least two of the processes to a common resource. ### Claim 9 Non-transitory computer-readable media containing a set of program instructions executable by hardware in a component and a spare component of a system, the component being configured to perform improved recovery by avoiding replaying of non-deterministic events, comprising: a recovery manager programmed to respond to a failure of the component after the component has undergone at least one programmed and replayable non-deterministic event internal to a processing node of the component since a most recent recording of a state of the component in a storage medium, and before the non-deterministic event is communicated to other components external to the processing node, by recovering the most recent state of the component from the storage medium, independent of an operating system, and loading the recovered state into the spare component to continue performing the process based on the recovered state without replaying the at least one programmed non-deterministic event and communicating the non-deterministic event to other components external to the processing node, wherein the at least one programmed and replayable non-deterministic event comprises a determination of an order in which at least two threads will have access to a state variable. ### Claim 10 (depends on 9) The computer-readable media of claim 9 wherein the component is further configured to execute multiple threads. ### Claim 11 (depends on 10) The computer-readable media of claim 10 wherein at least two of the threads share a common state as the component transitions through the series of states. ### Claim 12 (depends on 11) The computer-readable media of claim 11 wherein the common state comprises an access by said at least two of the threads to a common resource. ### Claim 13 (depends on 9) The computer-readable media of claim 9 wherein the component is further configured to perform multiple processes in parallel, the processes resulting in the component transitioning through the series of states. ### Claim 14 (depends on 13) The computer-readable media of claim 13 wherein at least one of the processes comprises multiple threads. ### Claim 15 (depends on 14) The computer-readable media of claim 14 wherein at least two of the processes share a common state as the component transitions through the series of states. ### Claim 16 (depends on 15) The computer-readable media of claim 15 wherein the common state comprises an access by said at least two of the processes to a common resource. ### Claim 17 (depends on 9) The computer-readable media of claim 9 wherein the set of program instructions comprises a checkpoint library accessible to an application running on the hardware, the running of the application resulting in the component transitioning through the series of states. ### Claim 18 (depends on 17) The computer-readable media of claim 17 wherein the hardware supports an operating system, and wherein communications between the application and the operating system flow through the checkpoint library. ### Claim 19 A method for improved recovery by avoiding replaying of non-deterministic events, comprising; responding to a failure of a component after the component has undergone at least one programmed and replayable non-deterministic event internal to a processing node of the component since a most recent recording of a state of the component in a storage medium, and before the non-deterministic event is communicated to other components external to the processing node, by recovering the most recent state recorded in the storage medium, independent of an operating system of the system and without replaying the at least one programmed non-deterministic event internal to the processing node and communicated to other components external to the processing node; and loading the recovered state in a spare component configured to continue performing the process on the basis of the recovered state; wherein the at least one programmed and replayable non-deterministic event comprises a determination of an order in which at least two threads will have access to a state variable. ### Claim 20 (depends on 19) The method of claim 19, comprising performing a process having multiple threads. ### Claim 21 (depends on 20) The method of claim 20 wherein at least two of the threads share a common state as the component transitions through the series of states. ### Claim 22 (depends on 21) The method of claim 21 wherein the common state comprises accessing a common resource by said at least two of the threads. ### Claim 23 (depends on 19) The method of claim 19, comprising performing multiple processes in parallel, the processes resulting in the component transitioning through the series of states. ### Claim 24 (depends on 23) The method of claim 23 wherein at least two of the processes sharing a common state as the component transitions through the series of states. ### Claim 25 (depends on 24) The method of claim 24 wherein the common state comprises accessing a common resource by said at least two of the processes. ### Claim 26 A hardware component, configured to operate in a system, for improved recovery by avoiding replaying of non-deterministic events, comprising: first means to perform a process that transitions the first through a series of states; second means to respond to a failure of the first means after the first means has undergone at least one programmed and replayable non-deterministic event internal to a processing node of the first means since a most recent recording of a state of the component in a storage medium, and before the non-deterministic event is communicated to other components external to the processing node, by the most recent state of the component being recovered from the storage medium, independent of an operating system, and without the at least one programmed non-deterministic event internal to the processing node being replayed and communicated to other components external to the processing node; and a third means loaded with the recovered state configured to continue to perform the process on the basis of the recovered state; wherein the at least one programmed and replayable non-deterministic event comprises a determination of an order in which at least two threads will have access to a state variable. ### Claim 27 (depends on 26) The component of claim 26 wherein the means to perform the process that transitions through the series of states comprises a process having multiple threads. ### Claim 28 (depends on 27) The component of claim 27 wherein at least two of the threads share a common state. ### Claim 29 (depends on 28) The component of claim 28 wherein the common state comprises an access by said at least two of the threads to a common resource. ### Claim 30 (depends on 26) The component of claim 26 wherein the means to perform the process that transitions through the series of states comprises multiple processes performed in parallel. ### Claim 31 (depends on 30) The component of claim 30 wherein at least one of the processes comprises multiple threads. ### Claim 32 (depends on 30) The component of claim 30 wherein at least two of the processes share a common state as the component transitions through the series of states. ### Claim 33 (depends on 32) The system of claim 32 wherein the common state comprises an access by said at least two of the processes to a common resource.