# US 10,310,942 B2 · Memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,942 B2 - Document ID: US10310942B2 - Status: Granted - Kind: B2 - Application number: 15/459,294 - Filed: 2017-03-15 - Published: 2018-03-22 - Granted: 2019-06-04 - Earliest claimed: 2016-09-20 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Marie Takada; Masanobu Shirakawa - Web page: https://patentgrep.com/patent/US10310942B2 ## CPC - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 2207/2245: Memory devices with an internal cache buffer - G11C 2211/5632: Multilevel reading using successive approximation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes: a semiconductor memory device; and a controller. When receiving the first read instruction, the semiconductor memory device issues a strobe signal at a first timing to read data from the first memory cell and the second memory cell. When receiving the second read instruction, the semiconductor memory device sets the first memory cell to a non-read target and reads data from the second memory cell based on a strobe result of the data at the first timing. ## Claims ### Claim 1 A memory system comprising: a semiconductor memory device including a memory cell array; and a controller capable of issuing a first read instruction and a second read instruction different, from the first read instruction, wherein the memory cell array includes: a first memory cell and a second memory cell; a first bit line connected to the first memory cell; and a second bit line connected to the second memory cell, and wherein when receiving the first read instruction, the semiconductor memory device applies a first voltage to the first bit line and the second bit line and issues a strobe signal at a first timing to read data from the first memory cell and the second memory cell, and when receiving the second read instruction, the semiconductor memory device applies a second voltage different from the first voltage to the first bit line to set the first memory cell to a non-read target and applies the first voltage to the second bit line to read data from the second memory cell based on a strobe result of the data at the first timing. ### Claim 2 (depends on 1) The system according to claim 1, wherein when receiving the first read instruction, the semiconductor memory device issues a strobe signal at a second timing different from the first timing to read data from the first memory cell and the second, memory cell. ### Claim 3 (depends on 2) The system according to claim 2, wherein the second timing is later than the first timing. ### Claim 4 (depends on 2) The system according to claim 2, wherein the semiconductor memory device reads data in units of page, one page data is determined using a plurality of read levels, at the first timing, the data is determined using a first read level, and at the second timing, the data is determined using a second read level different from the first read level. ### Claim 5 (depends on 4) The system according to claim 4, wherein when the second read instruction is issued, the semiconductor memory device determines the data using the second read level without using the first read level. ### Claim 6 (depends on 5) The system according to claim 5, wherein the memory cell array further includes a word line connected to the first memory cell and the second memory cell, and when receiving the first read instruction, the semiconductor memory device applies a third voltage different from the first voltage and the second voltage to the word line at the second timing, and when receiving the second read instruction, the semiconductor memory device applies a fourth voltage different from the third voltage to the word line. ### Claim 7 (depends on 4) The system according to claim 4, wherein the first read instruction and the second read instruction designate the same page as a read target. ### Claim 8 (depends on 7) The system according to claim 7, wherein the number of issuing the strobe signal of the semiconductor memory device when receiving the first read instruction is larger than the number of issuing the strobe signal when receiving the second read instruction. ### Claim 9 (depends on 8) The system, according to claim 8, wherein the semiconductor memory device further includes a latch circuit configured to hold the strobe result at the first-timing, and when receiving the second read instruction, the semiconductor memory device outputs data based on a data read result from the second memory cell and the strobe result held by the latch circuit to the controller as data of one page. ### Claim 10 A memory system comprising: a semiconductor memory device including a memory cell array and configured to read data from the memory cell array in units of page; and a controller capable of issuing a first read instruction to read first page data from the semiconductor memory device and a second read instruction different from the first read instruction, wherein the one page data is determined using a plurality of read levels, when receiving the first read instruction, the semiconductor memory device issues a strobe signal a first number of times, and when receiving the second read instruction, the semiconductor memory device issues the strobe signal a second number of times, and the first number of times is a natural number not less than 2, and the second number of times is smaller than the first number of times. ### Claim 11 (depends on 10) The system according to claim 10, wherein the first page data is determined using N read levels, the semiconductor memory device issues the strobe signal N times when receiving the first read instruction, and N is a natural number not less than 2. ### Claim 12 (depends on 11) The system according to claim 11, wherein the semiconductor memory device applies voltages different from each other to a selected word line at each timing at which the strobe signal is issued N times. ### Claim 13 (depends on 12) The system according to claim 12, wherein the voltages applied to the selected word line correspond to the N read levels. ### Claim 14 (depends on 13) The system according to claim 13, wherein the semiconductor memory device issues the strobe signal M times when receiving the second read instruction, a voltage applied to the selected word line at a timing at which the strobe signal is issued M times is different from the voltages applied to the selected word line at, each timing at which the strobe signal is issued N times, and M is a natural number not less than 1. ### Claim 15 (depends on 14) The system according to claim 14, wherein the strobe signal issued M times corresponds to one of the N read levels, and for remaining read levels, a read result for the first read instruction is used. ### Claim 16 A memory system comprising: a semiconductor memory device including a memory cell array; and a controller capable of issuing a first read instruction to read data from the semiconductor memory device in units of page and a second read instruction different from the first read instruction, wherein the memory cell array includes: a first memory cell; and a first, word line connected to the first memory cell, and wherein when receiving the first read instruction from the controller, the semiconductor memory device sequentially applies a first voltage and a second voltage different from the first voltage to the first word line and strobes data for each voltage to determine data of a first page, and sets data obtained using the strobe result when the first voltage is used without using the strobe result when the second voltage is used, and when receiving the second read instruction from the controller, the semiconductor memory device applies a third voltage different from the first voltage and the second voltage to the first word line to strobe data, and determines data of the first page based on the strobe result and the data in the latch circuit. ### Claim 17 (depends on 16) The system according to claim 16, wherein the controller executes error detection processing of the determined data. ### Claim 18 (depends on 17) The system according to claim 17, wherein the controller detects an error in the data of the first page obtained in response to the first read instruction, and if the error is not corrected, issues the second read instruction. ### Claim 19 (depends on 18) The system according to claim 18, wherein the controller detects an error in the data of the first page obtained in response to the second read instruction, and if the error is not corrected, issues a third read instruction, and when the third read instruction is issued, a fourth voltage different from the first voltage, the second voltage, and the third voltage is applied to the word line to strobe the data, and the data of the first, page is determined based on the strobe result and the data, in latch circuit. ### Claim 20 (depends on 16) The system according to claim 16, wherein the first page is determined based on at least a first read level and a second read level, the first voltage and the second voltage correspond to the first read level and the second read level, the third voltage corresponds to the second read level, and when the second read instruction is received, data read using the first voltage is used as read data corresponding to the first read level.