# US 10,310,936 B2 · Temporary pipeline marking for processor error workarounds > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,936 B2 - Document ID: US10310936B2 - Status: Granted - Kind: B2 - Application number: 15/404,578 - Filed: 2017-01-12 - Published: 2017-05-04 - Granted: 2019-06-04 - Earliest claimed: 2015-03-09 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Erez Barak; Steven R. Carlough; Eyal Gonen; Juergen Haess; Silvia M. Mueller - Web page: https://patentgrep.com/patent/US10310936B2 ## CPC - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F 9/3867: {using instruction pipelines} - G06F 11/0721: {within a central processing unit [CPU]} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)} - G06F 11/142: {Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044)} - G06F 11/2028: {eliminating a faulty processor or activating a spare} - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 11/3466: {Performance evaluation by tracing or monitoring} - G06F 2201/805: Real-time - G06F 2201/82: Solving problems relating to consistency - G06F 2201/85: Active fault masking without idle spares - G06F 2201/86: Event-based monitoring - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction. ## Claims ### Claim 1 A method for temporary pipeline marking for processor error workarounds, the method comprising: monitoring an execution unit pipeline of a processor for an event that is predetermined to cause a stuck state that results in an errant instruction execution result due to the stuck state, wherein the event is associated with a programmable instruction operational code; marking the execution unit pipeline for a workaround action based on detecting the event; triggering a clearing action based on the marking of the execution unit pipeline, wherein the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code; and clearing the marking of the pipeline based on the triggering of the clearing action, wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction. ### Claim 2 (depends on 1) The method of claim 1, wherein the event comprises a pipeline flush event. ### Claim 3 (depends on 1) The method of claim 1, wherein the event comprises a rescind event. ### Claim 4 (depends on 1) The method of claim 1, wherein the clearing action comprises a complete purging of the execution unit pipeline. ### Claim 5 (depends on 1) The method of claim 1, wherein the same pipeline stage that results in the stuck state is prior to finish logic of the processor. ### Claim 6 A computer system for temporary pipeline marking for processor error workarounds, the computer system comprising: a processor configured to perform a method comprising: monitoring an execution unit pipeline of the processor for an event that is predetermined to cause a stuck state that results in an errant instruction execution result due to the stuck state, wherein the event is associated with a programmable instruction operational code; marking the execution unit pipeline for a workaround action based on detecting the event; triggering a clearing action based on the marking of the execution unit pipeline, wherein the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code; and clearing the marking of the pipeline based on the triggering of the clearing action, wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction. ### Claim 7 (depends on 6) The computer system of claim 6, wherein the event comprises a pipeline flush event. ### Claim 8 (depends on 6) The computer system of claim 6, wherein the event comprises a rescind event. ### Claim 9 (depends on 6) The computer system of claim 6, wherein the clearing action comprises a complete purging of the execution unit pipeline. ### Claim 10 (depends on 6) The computer system of claim 6, wherein the same pipeline stage that results in the stuck state is prior to finish logic of the processor. ### Claim 11 A computer program product for temporary pipeline marking for processor error workarounds, the computer program product comprising: a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code executable to perform: monitoring an execution unit pipeline of a processor for an event that is predetermined to cause a stuck state that results in an errant instruction execution result due to the stuck state, wherein the event is associated with a programmable instruction operational code; marking the execution unit pipeline for a workaround action based on detecting the event; triggering a clearing action based on the marking of the execution unit pipeline, wherein the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code; and clearing the marking of the pipeline based on the triggering of the clearing action, wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction. ### Claim 12 (depends on 11) The computer program product of claim 11, wherein the event comprises a pipeline flush event. ### Claim 13 (depends on 11) The computer program product of claim 11, wherein the event comprises a rescind event. ### Claim 14 (depends on 11) The computer program product of claim 11, wherein the clearing action comprises a complete purging of the execution unit pipeline. ### Claim 15 (depends on 11) The computer program product of claim 11, wherein the same pipeline stage that results in the stuck state is prior to finish logic of the processor.