# US 10,310,926 B2 · Data error detection in computing systems

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- Number: US 10,310,926 B2
- Document ID: US10310926B2
- Status: Granted
- Kind: B2
- Application number: 16/028,707
- Filed: 2018-07-06
- Published: 2018-11-01
- Granted: 2019-06-04
- Earliest claimed: 2016-08-25
- Assignees: Microsoft Technology Licensing, LLC
- Applicants: Microsoft Technology Licensing, LLC
- Inventors: Bryan Kelly; Mallik Bulusu; Tom Nguyen
- Web page: https://patentgrep.com/patent/US10310926B2

## CPC

- G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Embodiments of ensuring data integrity in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method includes receiving, at a memory controller, a data request from the persistent storage to copy data from the memory. In response to the received data request, the requested data is retrieved from the memory. The retrieved data contains data bits and corresponding error correcting bits. The method can also include determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits associated with the data bits. In response to determining that the retrieved data bits contain one or more data integrity errors, the memory controller can write data representing existence of the one or more data integrity errors into a memory location accessible by the processor for ensuring data integrity.

## Claims

### Claim 1

A computing device having a processor with a machine check register, a memory, a memory controller, and a persistent storage interconnected to one another, the memory containing instructions executable by the processor to cause the computing device to:
retrieve, with the memory controller, data from the memory, the retrieved data containing data bits to be persisted in the persistent storage and error correcting bits corresponding to the data bits;
determine, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits corresponding to the data bits; and
in response to determining that the retrieved data bits contain one or more data integrity errors, with the memory controller, write data representing existence of the one or more data integrity errors into the machine check register accessible by the processor when execution of an operating system by the processor on the computing device is suspended.

### Claim 2 (depends on 1)

The computing device of claim 1 wherein the memory contains additional instructions executable by the processor to cause the computing device to:
copy only the data bits of the retrieved data to the persistent storage; and
persist the data representing existence of the one or more data integrity errors in the persistent storage indicating the existence of the one or more integrity errors.

### Claim 3 (depends on 1)

The computing device of claim 1 wherein:
to determine whether the accessed data indicates that the data being copied include one or more data integrity errors includes to determine whether the accessed data indicates that the data being copied include one or more two flipped bits; and
the data representing existence of the one or more data integrity errors includes data indicating the existence of two flipped bits in the data copied to the persistent storage from the memory.

### Claim 4 (depends on 1)

The computing device of claim 1 wherein the memory contains additional instructions executable by the processor to cause the computing device to update an entry in a file in the persistent storage according to the data representing existence of the one or more data integrity errors written into the machine check register, the entry indicating the existence of the one or more data integrity errors in the data copied to the persistent storage from the memory.

### Claim 5 (depends on 1)

The computing device of claim 1 wherein the memory contains additional instructions executable by the processor to cause the computing device to create a file in the persistent storage, the created file including data indicating the existence of the one or more data integrity errors in the data copied to the persistent storage from the memory.

### Claim 6 (depends on 1)

The computing device of claim 1 wherein the memory contains additional instructions executable by the processor to cause the computing device to execute instructions to access the machine check register periodically while the operating system of the computing device is suspended, the executed instructions being a part of a software package independent of the operating system of the computing device.

### Claim 7 (depends on 1)

The computing device of claim 1 wherein the machine check register includes a set of model-specific registers in a processor cache of the processor.

### Claim 8 (depends on 1)

The computing device of claim 1 wherein the memory contains additional instructions executable by the processor to cause the computing device to:
detect a power failure of a main power supply associated with the processor or a request for a system shutdown; and
in response to the detected power failure or request for a system shutdown, transmit a persistence command to the persistent storage, the persistence command instructing the persistent storage to copy data from a portion of the memory designated as a software implemented non-volatile dual in-line memory module using power from an auxiliary power source.

### Claim 9 (depends on 1)

The computing device of claim 1 the memory contains additional instructions executable by the processor to cause the computing device to:
detect a power failure of a main power supply associated with the processor or a request for a system shutdown;
in response to the detected power failure of the main power supply or the request for a system shutdown,
transmit a persistence command to the persistent storage, the persistence command instructing the persistent storage to copy data from the main memory using power from an auxiliary power source;
receive an indication from the persistent storage that data persistence is completed; and
in response to receiving the indication, allow the computing device to shut down.

### Claim 10 (depends on 1)

The computing device of claim 1 wherein the one or more data integrity errors are second one or more data integrity errors, and wherein the memory contains additional instructions executable by the processor to cause the computing device to:
retrieve, with the memory controller, additional data from the memory, the retrieved additional data containing data bits and error correcting bits corresponding to the data bits;
determine, at the memory controller, whether the retrieved data bits contain one or more first data integrity errors based on the error correcting bits corresponding to the data bits; and
in response to determining that the retrieved data bits contain one or more first data integrity errors,
suspend the operating system in the computing device; and
persist the data in the memory by performing the to retrieve, to determine, and to write operations.

### Claim 11

A method for ensuring data integrity in a computing device having a main processor with a processor cache, a memory controller, a volatile memory, and a persistent storage operatively interconnected to one another, the method comprising:
retrieving, with the memory controller, data from the memory, the retrieved data containing data bits to be persisted in the persistent storage and error correcting bits corresponding to the data bits;
determining, at the memory controller, whether the retrieved data bits contain one or more data integrity errors based on the error correcting bits corresponding to the data bits; and
in response to determining that the retrieved data bits contain one or more data integrity errors, with the memory controller, writing data representing existence of the one or more data integrity errors into the machine check register accessible by the processor when execution of an operating system by the processor on the computing device is suspended.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
copying only the data bits of the retrieved data to the persistent storage; and
persisting the data representing existence of the one or more data integrity errors in the persistent storage indicating the existence of the one or more integrity errors.

### Claim 13 (depends on 11)

The method of claim 11 wherein:
determining whether the accessed data indicates that the data being copied include one or more data integrity errors includes determining whether the accessed data indicates that the data being copied include one or more two flipped bits; and
the data representing existence of the one or more data integrity errors includes data indicating the existence of two flipped bits in the data copied to the persistent storage from the memory.

### Claim 14 (depends on 11)

The method of claim 11, further comprising updating an entry in a file in the persistent storage according to the data representing existence of the one or more data integrity errors written into the machine check register, the entry indicating the existence of the one or more data integrity errors in the data copied to the persistent storage from the memory.

### Claim 15 (depends on 11)

The method of claim 11, further comprising creating a file in the persistent storage, the created file including data indicating the existence of the one or more data integrity errors in the data copied to the persistent storage from the memory.

### Claim 16 (depends on 11)

The method of claim 11, further comprising executing instructions to access the machine check register periodically while the operating system of the computing device is suspended, the executed instructions being a part of a software package independent of the operating system of the computing device.

### Claim 17 (depends on 11)

The method of claim 11 wherein the machine check register includes a set of model-specific registers in a processor cache of the processor.

### Claim 18 (depends on 11)

The method of claim 11, further comprising:
detecting a power failure of a main power supply associated with the processor or a request for a system shutdown; and
in response to the detected power failure or request for a system shutdown, transmitting a persistence command to the persistent storage, the persistence command instructing the persistent storage to copy data from a portion of the memory designated as a software implemented non-volatile dual in-line memory module using power from an auxiliary power source.

### Claim 19 (depends on 11)

The method of claim 11, further comprising:
detecting a power failure of a main power supply associated with the processor or a request for a system shutdown;
in response to the detected power failure of the main power supply or the request for a system shutdown,
transmitting a persistence command to the persistent storage, the persistence command instructing the persistent storage to copy data from the main memory using power from an auxiliary power source;
receiving an indication from the persistent storage that data persistence is completed; and
in response to receiving the indication, allowing the computing device to shut down.

### Claim 20 (depends on 11)

The method of claim 11 wherein the one or more data integrity errors are second one or more data integrity errors, and wherein the method further includes:
retrieving, with the memory controller, additional data from the memory, the retrieved additional data containing data bits and error correcting bits corresponding to the data bits;
determining, at the memory controller, whether the retrieved data bits contain one or more first data integrity errors based on the error correcting bits corresponding to the data bits; and
in response to determining that the retrieved data bits contain one or more first data integrity errors,
suspending the operating system in the computing device; and
persisting the data in the memory by performing the to retrieve, to determine, and to write operations.