# US 10,310,897 B2 · Hardware accelerators and methods for offload operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,897 B2 - Document ID: US10310897B2 - Status: Granted - Kind: B2 - Application number: 15/282,372 - Filed: 2016-09-30 - Published: 2018-04-05 - Granted: 2019-06-04 - Earliest claimed: 2016-09-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Tracy Garrett Drysdale; Vinodh Gopal; James D. Guilford - Web page: https://patentgrep.com/patent/US10310897B2 ## CPC - G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU] - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/5044: {considering hardware capabilities} - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F 2209/509: Offload - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatuses relating to offload operations are described. In one embodiment, a hardware processor includes a core to execute a thread and offload an operation; and a first and second hardware accelerator to execute the operation, wherein the first and second hardware accelerator are coupled to shared buffers to store output data from the first hardware accelerator and provide the output data as input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer. ## Claims ### Claim 1 A hardware processor comprising: a core to execute a thread and offload an operation; a plurality of shared buffers; and a first hardware accelerator and a second hardware accelerator to execute the operation to generate output data and consume input data, wherein the first hardware accelerator and the second hardware accelerator are coupled to the plurality of shared buffers to store the output data from the first hardware accelerator and provide the output data as the input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer, wherein the second hardware accelerator is to compare a pointer for a last valid input entry of the input buffer descriptor array to a pointer for a last consumed input response entry of the input buffer response descriptor array to determine when the second hardware accelerator is to execute to consume the input data from the plurality of shared buffers, and the first hardware accelerator is to compare a pointer for a last valid output entry of the output buffer descriptor array to a pointer for a last consumed output response entry of the output buffer response descriptor array to determine when the first hardware accelerator is to execute to generate the output data into the plurality of shared buffers. ### Claim 2 (depends on 1) The hardware processor of claim 1, wherein the second hardware accelerator is to perform the compare and the first hardware accelerator is to perform the compare without involvement from the core. ### Claim 3 (depends on 1) The hardware processor of claim 1, wherein the core is to allocate the plurality of shared buffers, and load the entries in the input buffer descriptor array for each respective shared buffer. ### Claim 4 (depends on 3) The hardware processor of claim 3, wherein the core is to load the entries in the output buffer descriptor array for each respective shared buffer. ### Claim 5 (depends on 1) The hardware processor of claim 1, wherein the first hardware accelerator is to load the plurality of shared buffers with the output data and load the corresponding response entries in the output buffer response descriptor array for each respective shared buffer consumed. ### Claim 6 (depends on 5) The hardware processor of claim 5, wherein the second hardware accelerator is to load the corresponding response entries in the input buffer response descriptor array for each respective shared buffer consumed. ### Claim 7 (depends on 1) The hardware processor of claim 1, wherein the entries in the input buffer descriptor array each include a size of the input data stored in the respective shared buffer, the corresponding response entries in the input buffer response descriptor array each include a size of the input data remaining in the respective shared buffer, the entries in the output buffer descriptor array each include a size of the respective shared buffer available to store output data, and the corresponding response entries in the output buffer response descriptor array each include a size of the output data stored in the respective shared buffer. ### Claim 8 A method comprising: offloading an operation from a hardware processor to a first hardware accelerator; executing the operation on the first hardware accelerator and a second hardware accelerator to generate output data and consume input data, wherein the first hardware accelerator and the second hardware accelerator are coupled to a plurality of shared buffers to store the output data from the first hardware accelerator and provide the output data as the input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer; comparing a pointer for a last valid input entry of the input buffer descriptor array to a pointer for a last consumed input response entry of the input buffer response descriptor array with the second hardware accelerator to determine when the second hardware accelerator is to execute to consume the input data from the plurality of shared buffers; and comparing a pointer for a last valid output entry of the output buffer descriptor array to a pointer for a last consumed output response entry of the output buffer response descriptor array with the first hardware accelerator to determine when the first hardware accelerator is to execute to generate the output data into the plurality of shared buffers. ### Claim 9 (depends on 8) The method of claim 8, wherein the second hardware accelerator performs the comparing and the first hardware accelerator performs the comparing without involvement from the hardware processor. ### Claim 10 (depends on 8) The method of claim 8, further comprising allocating the plurality of shared buffers, and loading the entries in the input buffer descriptor array for each respective shared buffer. ### Claim 11 (depends on 10) The method of claim 10, further comprising loading the entries in the output buffer descriptor array for each respective shared buffer. ### Claim 12 (depends on 8) The method of claim 8, further comprising loading the plurality of shared buffers with the output data and loading the corresponding response entries in the output buffer response descriptor array for each respective shared buffer consumed. ### Claim 13 (depends on 12) The method of claim 12, further comprising loading the corresponding response entries in the input buffer response descriptor array for each respective shared buffer consumed. ### Claim 14 (depends on 8) The method of claim 8, further comprising providing the entries in the input buffer descriptor array that each include a size of the input data stored in the respective shared buffer, the corresponding response entries in the input buffer response descriptor array that each include a size of the input data remaining in the respective shared buffer, the entries in the output buffer descriptor array that each include a size of the respective shared buffer available to store output data, and the corresponding response entries in the output buffer response descriptor array that each include a size of the output data stored in the respective shared buffer. ### Claim 15 A system comprising: a hardware processor to execute a thread and offload an operation; a plurality of shared buffers; and a first hardware accelerator and a second hardware accelerator to execute the operation to generate output data and consume input data, wherein the first hardware accelerator and the second hardware accelerator are coupled to the plurality of shared buffers to store the output data from the first hardware accelerator and provide the output data as the input data to the second hardware accelerator, an input buffer descriptor array of the second hardware accelerator with an entry for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator with a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator with an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator with a corresponding response entry for each respective shared buffer, wherein the second hardware accelerator is to compare a pointer for a last valid input entry of the input buffer descriptor array to a pointer for a last consumed input response entry of the input buffer response descriptor array to determine when the second hardware accelerator is to execute to consume the input data from the plurality of shared buffers, and the first hardware accelerator is to compare a pointer for a last valid output entry of the output buffer descriptor array to a pointer for a last consumed output response entry of the output buffer response descriptor array to determine when the first hardware accelerator is to execute to generate the output data into the plurality of shared buffers. ### Claim 16 (depends on 15) The system of claim 15, wherein the second hardware accelerator is to perform the compare and the first hardware accelerator is to perform the compare without involvement from the hardware processor. ### Claim 17 (depends on 15) The system of claim 15, wherein the hardware processor is to allocate the plurality of shared buffers, and load the entries in the input buffer descriptor array for each respective shared buffer. ### Claim 18 (depends on 17) The system of claim 17, wherein the hardware processor is to load the entries in the output buffer descriptor array for each respective shared buffer. ### Claim 19 (depends on 15) The system of claim 15, wherein the first hardware accelerator is to load the plurality of shared buffers with the output data and load the corresponding response entries in the output buffer response descriptor array for each respective shared buffer consumed. ### Claim 20 (depends on 19) The system of claim 19, wherein the second hardware accelerator is to load the corresponding response entries in the input buffer response descriptor array for each respective shared buffer consumed. ### Claim 21 (depends on 15) The system of claim 15, wherein the entries in the input buffer descriptor array each include a size of the input data stored in the respective shared buffer, the corresponding response entries in the input buffer response descriptor array each include a size of the input data remaining in the respective shared buffer, the entries in the output buffer descriptor array each include a size of the respective shared buffer available to store output data, and the corresponding response entries in the output buffer response descriptor array each include a size of the output data stored in the respective shared buffer.