# US 10,310,895 B2 · Memory-based software barriers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,895 B2 - Document ID: US10310895B2 - Status: Granted - Kind: B2 - Application number: 15/493,670 - Filed: 2017-04-21 - Published: 2018-10-25 - Granted: 2019-06-04 - Earliest claimed: 2017-04-21 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Altug Koker; Joydeep Ray; Balaji Vembu; James A. Valerio; Abhishek R. Appu - Web page: https://patentgrep.com/patent/US10310895B2 ## CPC - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/522: {Barrier synchronisation} - G06T 1/60: Memory management - G06T 2210/52: Parallel processing - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers. ## Claims ### Claim 1 An apparatus comprising: one or more processors including a graphics processor, the graphics processor including a plurality of hardware barriers; and a graphics data port unit; wherein the one or more processors are to: schedule a plurality of threads for processing, including assigning one or more hardware barriers of the plurality of hardware barriers to one or more thread groups; track barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier; upon determining based on the tracking of barrier resources that a number of available hardware barriers is insufficient for scheduling of threads, assign one or more software barriers to a first thread group to emulate operation of one or more hardware barriers; perform handling of the one or more software barriers in the graphics processor using the graphics data port unit without necessitating changes to an application programming interface (API) or a compiler associated with the one or more processors; and transmit a barrier message to the graphics data port unit, the barrier message including one or more attribute bits to indicate the one or more software barriers and including a respective memory address for each of the one or more software barriers. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more software barriers comprise memory-based software barriers, and wherein the one or more processors are further to use global memory locations to implement the memory-based software barriers in software. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the one or more processors are further to perform atomic operations to update the memory-based software barriers. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the graphics processor is co-located with an application processor on a common semiconductor package. ### Claim 5 A method comprising: scheduling a plurality of threads for processing at one or more processors including a graphics processor, the graphics processor including a plurality of hardware barriers, wherein scheduling includes assigning one or more hardware barriers of the plurality of hardware barriers to one or more thread groups; tracking barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier; upon determining based on the tracking of barrier assignments that a number of available hardware barriers is insufficient for scheduling of threads, assigning one or more software barriers to a first thread group to emulate operation of one or more hardware barriers; performing handling of the one or more software barriers in the graphics processor using a graphics data port unit without necessitating changes to an application programming interface (API) or a compiler associated with the one or more processors; and transmitting a barrier message to the graphics data port unit, the barrier message including one or more attribute bits to indicate the one or more software barriers and including a respective memory address for each of the one or more software barriers. ### Claim 6 (depends on 5) The method of claim 5, wherein the one or more software barriers comprise one or more memory-based software barriers using global memory locations to implement the memory-based software barriers in software. ### Claim 7 (depends on 6) The method of claim 6, further comprising performing atomic operations to update the memory-based software barriers. ### Claim 8 (depends on 5) The method of claim 5, wherein the graphics processor is co-located with an application processor on a common semiconductor package. ### Claim 9 At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising: scheduling a plurality of threads for processing at one or more processors including a graphics processor, the graphics processor including a plurality of hardware barriers, wherein scheduling includes assigning one or more hardware barriers of the plurality of hardware barriers to one or more thread groups; tracking barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier; upon determining based on the tracking of barrier resources that a number of available hardware barriers is insufficient for scheduling of threads, assign one or more software barriers to a first thread group to emulate operation of one or more hardware barriers; performing handling of the one or more software barriers in the graphics processor using a graphics data port unit without necessitating changes to an application programming interface (API) or a compiler associated with the processor; and transmitting a barrier message to the graphics data port unit, the barrier message including one or more attribute bits to indicate the one or more software barriers and including a respective memory address for each of the one or more software barriers. ### Claim 10 (depends on 9) The at least one machine-readable medium of claim 9, wherein the one or more software barriers comprise one or more memory-based software barriers using global memory locations to implement the memory-based software barriers in software. ### Claim 11 (depends on 10) The at least one machine-readable medium of claim 10, further comprising instructions to perform operations comprising: performing atomic operations to update the memory-based software barriers. ### Claim 12 (depends on 9) The at least one machine-readable medium of claim 9, wherein the graphics processor is co-located with an application processor on a common semiconductor package. ### Claim 13 (depends on 2) The apparatus of claim 2, further comprising a thread register, wherein the one or more processors are to store a respective memory address for each of the one or more software barriers in the thread register and are to set a bit for each stored memory address, the bit to indicate whether data relates to a hardware barrier or a software barrier. ### Claim 14 (depends on 5) The method of claim 5, further comprising storing a respective memory address for each of the one or more software barriers in a thread register and setting a bit for each stored memory address, the bit to indicate whether data relates to a hardware barrier or a software barrier.