# US 10,310,882 B2 · Algorithm and apparatus to deploy virtual machine monitor on demand > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,882 B2 - Document ID: US10310882B2 - Status: Granted - Kind: B2 - Application number: 15/172,529 - Filed: 2016-06-03 - Published: 2016-09-29 - Granted: 2019-06-04 - Earliest claimed: 2013-03-12 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Thomas Zeng; Azzedine Touzni; Philip Mueller, Jr.; Piyush Patel - Web page: https://patentgrep.com/patent/US10310882B2 ## CPC - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/45533: {Hypervisors; Virtual machine monitors} - G06F 9/45545: {Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox} - G06F 9/5016: {the resource being the memory} - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings} - G06F 21/44: Program or device authentication - G06F 21/53: by executing in a restricted environment, e.g. sandbox or secure virtual machine - G06F 12/10: Address translation - G06F 2009/45583: {Memory management, e.g. access or allocation} - G06F 2009/45587: {Isolation or security of virtual machine instances} - G06F 2212/1052: Security improvement - G06F 2212/151: Emulated environment, e.g. virtual machine - G06F 2212/152: Virtualized environment, e.g. logically partitioned system - G06F 2212/68: Details of translation look-aside buffer [TLB] - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by selectively enabling a hypervisor operating on a computing device during sandbox sessions. In the various aspects, a high-level operating system may allocate memory such that its intermediate physical addresses are equal to the physical addresses. When the hypervisor is disabled, the hypervisor may suspend second stage translations from intermediate physical addresses to physical addresses. During a sandbox session, the hypervisor may be enabled and resume performing second stage translations. ## Claims ### Claim 1 A method of managing memory on a computing device, comprising: initializing a hypervisor, a security monitor, and a high-level operating system (HLOS); disabling the hypervisor after initialization; monitoring for a signal from the security monitor to start a sandbox session; enabling the hypervisor in response to receiving the signal to start the sandbox session; implementing access control while the hypervisor is enabled; and allocating memory by the HLOS so that an intermediate physical address in the HLOS's intermediate physical address space is the same as a physical address in a physical address space and so that a virtual address in the HLOS's virtual address space is mapped to the physical address via the intermediate physical address when the hypervisor is enabled and when the hypervisor is disabled. ### Claim 2 (depends on 1) The method of claim 1, wherein the security monitor is developed by ARM®. ### Claim 3 (depends on 1) The method of claim 1, wherein the hypervisor may be disabled or enabled across at least one of an integrated circuit boundary and a chip boundary. ### Claim 4 (depends on 1) The method of claim 1, wherein initializing the hypervisor comprises configuring the HLOS to allocate memory space such that each intermediate physical address in the HLOS's intermediate physical address space is equal to a corresponding physical address in the physical address space. ### Claim 5 (depends on 4) The method of claim 4, wherein initializing the hypervisor further comprises authenticating the hypervisor's code and data with the security monitor. ### Claim 6 (depends on 5) The method of claim 5, further comprising configuring the hypervisor's code and data to be inaccessible to at least one of a digital signal processor and a central processing unit (CPU) included in the digital signal processor while the hypervisor is enabled. ### Claim 7 (depends on 1) The method of claim 1, wherein implementing access control comprises implementing second stage translations. ### Claim 8 A computing device, comprising: a memory; and a processor coupled to the memory, wherein the processor is configured with processor-executable instructions to perform operations comprising: initializing a hypervisor, a security monitor, and a high-level operating system (HLOS); disabling the hypervisor after initialization; monitoring for a signal from the security monitor to start a sandbox session; enabling the hypervisor in response to receiving the signal to start the sandbox session; implementing access control while the hypervisor is enabled; and allocating memory by the HLOS so that an intermediate physical address in the HLOS's intermediate physical address space is the same as a physical address in a physical address space and so that a virtual address in the HLOS's virtual address space is mapped to the physical address via the intermediate physical address when the hypervisor is enabled and when the hypervisor is disabled. ### Claim 9 (depends on 8) The computing device of claim 8, wherein the security monitor is developed by ARM®. ### Claim 10 (depends on 8) The computing device of claim 8, wherein the processor is configured with processor-executable instructions to perform operations such that the hypervisor may be disabled or enabled across at least one of an integrated circuit boundary and a chip boundary. ### Claim 11 (depends on 8) The computing device of claim 8, wherein the processor is configured with processor-executable instructions to perform operations such that initializing the hypervisor comprises configuring the HLOS to allocate memory space such that each intermediate physical address in the HLOS's intermediate physical address space is equal to a corresponding physical address in the physical address space. ### Claim 12 (depends on 11) The computing device of claim 11, wherein the processor is configured with processor-executable instructions to perform operations such that initializing the hypervisor further comprises authenticating the hypervisor's code and data with the security monitor. ### Claim 13 (depends on 12) The computing device of claim 12, wherein the processor is configured with processor-executable instructions to perform operations further comprising configuring the hypervisor's code and data to be inaccessible to at least one of a digital signal processor and a central processing unit (CPU) included in the digital signal processor while the hypervisor is enabled. ### Claim 14 (depends on 8) The computing device of claim 8, wherein the processor is configured with processor-executable instructions to perform operations such that implementing access control comprises implementing second stage translations. ### Claim 15 A computing device, comprising: means for initializing a hypervisor, a security monitor, and a high-level operating system (HLOS); means for disabling the hypervisor after initialization; means for monitoring for a signal from the security monitor to start a sandbox session; means for enabling the hypervisor in response to receiving the signal to start the sandbox session; means for implementing access control while the hypervisor is enabled; and means for allocating memory by the HLOS so that an intermediate physical address in the HLOS's intermediate physical address space is the same as a physical address in a physical address space and so that a virtual address in the HLOS 's virtual address space is mapped to the physical address via the intermediate physical address when the hypervisor is enabled and when the hypervisor is disabled. ### Claim 16 (depends on 15) The computing device of claim 15, wherein the security monitor is developed by ARM®. ### Claim 17 (depends on 15) The computing device of claim 15, wherein the hypervisor may be disabled or enabled across at least one of an integrated circuit boundary and a chip boundary. ### Claim 18 (depends on 15) The computing device of claim 15, wherein means for initializing the hypervisor comprises means for configuring the HLOS to allocate memory space such that each intermediate physical address in the HLOS's intermediate physical address space is equal to a corresponding physical address in the physical address space. ### Claim 19 (depends on 18) The computing device of claim 18, wherein means for initializing the hypervisor further comprises means for authenticating the hypervisor's code and data with the security monitor. ### Claim 20 (depends on 19) The computing device of claim 19, further comprising means for configuring the hypervisor's code and data to be inaccessible to at least one of a digital signal processor and a central processing unit (CPU) included in the digital signal processor while the hypervisor is enabled. ### Claim 21 (depends on 15) The computing device of claim 15, wherein means for implementing access control comprises means for implementing second stage translations. ### Claim 22 A non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations for managing memory on a computing device, the operations comprising: initializing a hypervisor, a security monitor, and a high-level operating system (HLOS); disabling the hypervisor after initialization; monitoring for a signal from the security monitor to start a sandbox session; enabling the hypervisor in response to receiving the signal to start the sandbox session; implementing access control while the hypervisor is enabled; and allocating memory by the HLOS so that an intermediate physical address in the HLOS's intermediate physical address space is the same as a physical address in a physical address space and so that a virtual address in the HLOS's virtual address space is mapped to the physical address via the intermediate physical address when the hypervisor is enabled and when the hypervisor is disabled. ### Claim 23 (depends on 22) The non-transitory processor-readable storage medium of claim 22, wherein the security monitor is developed by ARM®. ### Claim 24 (depends on 22) The non-transitory processor-readable storage medium of claim 22, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that the hypervisor may be disabled or enabled across at least one of an integrated circuit boundary and a chip boundary. ### Claim 25 (depends on 22) The non-transitory processor-readable storage medium of claim 22, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that initializing the hypervisor comprises configuring the HLOS to allocate memory space such that each intermediate physical address in the HLOS's intermediate physical address space is equal to a corresponding physical address in the physical address space. ### Claim 26 (depends on 25) The non-transitory processor-readable storage medium of claim 25, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that initializing the hypervisor further comprises authenticating the hypervisor's code and data with the security monitor. ### Claim 27 (depends on 26) The non-transitory processor-readable storage medium of claim 26, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations further comprising configuring the hypervisor's code and data to be inaccessible to at least one of a digital signal processor and a central processing unit (CPU) included in the digital signal processor while the hypervisor is enabled. ### Claim 28 (depends on 22) The non-transitory processor-readable storage medium of claim 22, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that implementing access control comprises implementing second stage translations.