# US 10,310,860 B2 · Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor

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- Number: US 10,310,860 B2
- Document ID: US10310860B2
- Status: Granted
- Kind: B2
- Application number: 15/224,213
- Filed: 2016-07-29
- Published: 2018-02-01
- Granted: 2019-06-04
- Earliest claimed: 2016-07-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Wen-Tzer T. Chen; Diane G. Flemming; Sandy K. Kao; William A. Maron; Mysore S. Srinivas; Donald R. Stence; Calvin L. Sze
- Web page: https://patentgrep.com/patent/US10310860B2

## CPC

- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks}
- G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system and method adjust instruction dispatch in a multi-pipeline processor core having a plurality of execution units for improved performance of out-of-order execution of instructions. A dispatch adjust circuit receives a queue full signal from one or more of the execution queues that indicates the corresponding execution queue is full. In response to the queue full signal, the instruction dispatch circuit sends a stop signal to the instruction issuer to stop issuing additional instructions to the queues until one or more of the queues are empty. The dispatch adjust circuit may also receive a queue empty signal from the queues to detect when they are empty to send a start signal to the issuer.

## Claims

### Claim 1

A computer processor core comprising:
an issuer for issuing decoded instructions;
a plurality of queues that receive the decoded instructions from the issuer;
a dispatcher that dispatches the decoded instructions from the plurality of queues to a plurality of execution units; and
a dispatch adjust circuit that receives queue full signals comprising a queue full signal from each of the plurality of queues and in response to the queue full signals sends a stop signal;
wherein the issuer, in response to the stop signal, stops sending decoded instructions to the plurality of queues; and
wherein the dispatch adjust circuit further receives queue empty signals comprising a queue empty signal from each of the plurality of queues, and in response to the queue empty signals indicating all of the plurality of queues are empty, sends a start signal to restart sending decoded instructions to the plurality of queues.

### Claim 2 (depends on 1)

The computer processor core of claim 1 wherein the dispatch adjust circuit is in the dispatcher.

### Claim 3 (depends on 1)

The computer processor core of claim 1 wherein the dispatch adjust circuit is in the issuer.

### Claim 4 (depends on 1)

The computer processor core of claim 1 wherein the processor core is one of a plurality of processor cores integrated into a single integrated circuit processor chip.

### Claim 5 (depends on 1)

The computer processor core of claim 1 wherein the processor core comprises a multi-pipeline processor core with out-of-order execution of instructions.

### Claim 6

A method for issuing instructions in a computer processor core, the method comprising:
monitoring a plurality of queues being loaded with decoded instructions;
determining when at least one of the plurality of queues is full;
when the at least one of the plurality of queues is full, stopping loading the plurality of queues by sending a stop signal to an instruction issuer to stop issuing instructions;
monitoring the plurality of queues for emptiness;
determining when the plurality of queues is empty; and
when the plurality of queues is empty, sending a start signal to restart sending instructions to the plurality of queues.

### Claim 7 (depends on 6)

The method of claim 6 wherein the stop signal is sent when all of the plurality of queues are full.

### Claim 8 (depends on 6)

The method of claim 6 wherein the steps are performed by a dispatch adjust circuit in an instruction issuer in the computer processor core.

### Claim 9 (depends on 6)

The method of claim 6 wherein the steps are performed by a dispatch adjust circuit in an instruction dispatcher in the computer processor core.

### Claim 10 (depends on 6)

The method of claim 6 wherein the computer processor core is one of a plurality of processor cores integrated into a single integrated circuit processor chip.

### Claim 11 (depends on 6)

The method of claim 6 wherein the computer processor core comprises a multi-pipeline processor core with out-of-order execution of instructions.