# US 10,310,809 B2 · Apparatus and method for supporting a conversion instruction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,809 B2 - Document ID: US10310809B2 - Status: Granted - Kind: B2 - Application number: 15/093,947 - Filed: 2016-04-08 - Published: 2017-10-12 - Granted: 2019-06-04 - Earliest claimed: 2016-04-08 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: David Raymond Lutz; Neil Burgess; Kelvin Domnic Goveas - Web page: https://patentgrep.com/patent/US10310809B2 ## CPC - G06F 5/015: {having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence)} - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 9/30014: {with variable precision} - G06F 9/30025: {Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion} - H03M 7/24: Conversion to or from floating-point codes - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A data processing system includes instruction decoder circuitry responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry performs a right shift upon at least part of the input number and left shifting circuitry performs a left shift of at least part of the input number. Selection circuitry serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated. ## Claims ### Claim 1 Apparatus for processing data comprising: processing circuitry to perform one or more processing operations specified by program instruction; and an instruction decoder to decode said program instructions to generate one or more control signals to control said processing circuitry to perform processing operations specified by said program instruction; wherein said program instruction includes a conversion instruction to convert an input number to an output number; said processing circuitry comprises: right shifting circuitry to perform a right shift upon at least part of said input number to generate a right shifted number in response to said instruction decoder decoding said conversion instruction; left shifting circuitry to perform a left shift upon at least part of said input number to generate a left shifted number in response to said instruction decoder decoding said conversion instruction; and selection circuitry to select one of said right shifted number and said left shifted number as a selected shifted number to form at least part of said output number; wherein said input number is a floating-point number having an exponent value E and a significand value S, and said output number is an N-bit integer number having an integer value; wherein said selection circuitry is configured to select said left shifted number as said selected shifted number when said floating point number is greater than a maximum number representable as said integer number; and wherein in response to said conversion instruction, said instruction decoder is configured to control both the right shifting circuitry to perform the right shift and the left shifting circuitry to perform the left shift. ### Claim 2 (depends on 1) Apparatus as claimed in claim 1, wherein said right shifting circuitry is responsive to said exponent value to right shift at least part of said significand value by a right shift amount dependent upon said exponent value; and said right shift amount shifts any bits within said significand having a same bit significance as a bit position within said integer value to a bit position within said right shifted number matching said bit position within said integer number. ### Claim 3 (depends on 2) Apparatus as claimed in claim 2, wherein said right shifting circuitry sets to zero any bit positions within said right shifted number without bits shifted thereto from said significand value by said right shift amount. ### Claim 4 (depends on 2) Apparatus as claimed in claim 2, wherein said right shift amount is (N−1)−E. ### Claim 5 (depends on 1) Apparatus as claimed in claim 1, wherein said left shifting circuitry is responsive to said exponent value to left shift at least part of said significand value by a left shift amount dependent upon said exponent value; and said left shift amount shifts any bits within said significand having a same bit significance as a bit position within said integer value to a bit position within said left shifted number matching said bit position within said integer number. ### Claim 6 (depends on 5) Apparatus as claimed in claim 5, wherein said left shifting circuitry sets to zero any bit positions within said left shifted number without bits shifted thereto from said significand value by said left shift amount. ### Claim 7 (depends on 5) Apparatus as claimed in claim 5, wherein said left shift amount is E−(N−1). ### Claim 8 (depends on 1) Apparatus as claimed in claim 1, wherein said selection circuitry selects said right shifted number as said selected shifted number when said floating point number is equal to or less than a maximum number representable as said integer number. ### Claim 9 (depends on 1) Apparatus as claimed in claim 1, wherein said processing circuitry comprises two's-complement circuitry to perform a two's complement operation upon said selected shifted number when said input number is negative. ### Claim 10 (depends on 1) Apparatus as claimed in claim 1, wherein said processing circuitry comprises truncation circuitry to form as said output number a least significant bit portion of said selected shifted number. ### Claim 11 (depends on 1) Apparatus as claimed in claim 1, said processing circuitry comprises truncation circuitry to form as said output number a least significant N bits of said selected shifted number. ### Claim 12 (depends on 1) Apparatus as claimed in claim 1, wherein in response to said conversion instruction, said instruction decoder is configured to control the right shifting circuitry to perform the right shift in parallel with the left shifting circuitry performing the left shift. ### Claim 13 A method of processing data comprising: performing one or more processing operations specified by program instruction; and decoding said program instruction to generate one or more control signals to control performance of processing operations specified by said program instruction; wherein said program instruction includes a conversion instruction to convert an input number to an output number, which when decoded, generates one or more control signals to control performance of the processing operations including: performing a right shift upon at least part of said input number to generate a right shifted number in response to decoding of said conversion instruction; performing a left shift upon at least part of said input number to generate a left shifted number in response to decoding of said conversion instruction; and selecting one of said right shifted number and said left shifted number as a selected shifted number to form at least part of said output number; wherein said input number is a floating-point number having an exponent value E and a significand value S, and said output number is an N-bit integer number having an integer value; wherein said selecting includes selecting said left shifted number as said selected shifted number when said floating point number is greater than a maximum number representable as said integer number; and wherein both the right shift and the left shift are performed in response to the same conversion instruction.