# US 10,310,772 B2 · Memory control method and memory control apparatus

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- Number: US 10,310,772 B2
- Document ID: US10310772B2
- Status: Granted
- Kind: B2
- Application number: 15/361,295
- Filed: 2016-11-25
- Published: 2017-05-25
- Granted: 2019-06-04
- Earliest claimed: 2015-11-24
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Shi Cong Zhou
- Web page: https://patentgrep.com/patent/US10310772B2

## CPC

- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}
- G06F 3/0661: {Format or protocol conversion arrangements}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 16/10: Programming or data input circuits
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure provides memory control methods and memory control apparatus. An exemplary method includes providing a memory having a targeted memory zone, the targeted memory zone having a plurality of memory cells, and a storage capacity of each memory cell being one page; receiving and reading out to-be-stored data and obtaining the targeted address information of the to-be-stored data; reading out data status of all memory cells of a targeted memory zone; determining the data status of the memory cells of the targeted memory zone; performing a programming operation to a memory cell with an erased state to write the to-be-stored data into the memory cell with the erased state; and performing an erasing operation to a memory cell having a logic address of written data to remove the logic address.

## Claims

### Claim 1

A memory control method, comprising:
providing a memory having a targeted memory zone, the targeted memory zone having a plurality of memory cells, and a storage capacity of each memory cell being one page;
receiving and reading out to-be-stored data and obtaining the targeted address information of the to-be-stored data;
reading out data status of each of the plurality of memory cells of the targeted memory zone, the data status of the each of the plurality of memory cells of the targeted memory zone being one of an erased state, an indefinite state, and an active state;
determining the data status of the each of the plurality of memory cells of the targeted memory zone;
performing a programming operation to a memory cell with the erased state to write the to-be-stored data into the memory cell with the erased state; and
performing an erasing operation to a memory cell having a logic address of written data, wherein:
two memory cells of the plurality of memory cells of the targeted memory zone are at the valid state and have a same logic address, and
an erasing operation is performed to a memory cell with a larger serial number before performing the programming operation.

### Claim 2 (depends on 1)

The memory control method according to claim 1, wherein:
one memory cell of the targeted memory zone is at the erased state; and
the programming operation is performed to the memory cell with the erased state.

### Claim 3 (depends on 1)

The memory control method according to claim 1, wherein:
one memory cell of the targeted memory zone is at the indefinite state; and
an erasing operation is performed to the memory cell with the indefinite state before performing the programming operation.

### Claim 4 (depends on 1)

The memory control method according to claim 1, wherein the to-be-stored-data comprises:
data information;
targeted address information; and
identification information of the data.

### Claim 5 (depends on 4)

The memory control method according to claim 4, wherein the to-be-stored data further comprises:
determining information.

### Claim 6 (depends on 1)

The memory control method according to claim 1, wherein:
the step of reading out data status of all the plurality of memory cells is performed before the step of receiving and reading out the to-be-stored data.

### Claim 7 (depends on 1)

The memory control method according to claim 1, wherein:
the step of reading out the data status in each of the plurality of memory cells is performed after the step of receiving and reading out the to-be-stored data.

### Claim 8 (depends on 1)

The memory control method according to claim 1, wherein:
the step of reading out the data status in each of the plurality of memory cells and the step of receiving and reading out the to-be-stored data are performed simultaneously.

### Claim 9

A control apparatus of a memory including a targeted memory zone having a plurality of memory cells, a storage capacity of each memory cell being one page, the apparatus comprising:
a first acquisition unit, configured to receive a to-be-stored data and obtain a targeted address of the to-be-stored data;
a read out unit, configured to read out data status of each of the plurality of memory cells of the target memory zone, the data status of the each of the plurality of memory cells of the targeted memory zone being one of an erased state, an indefinite state, and an active state;
a programming unit, configured to perform a programming operation to a memory cell with the erased status and write the to-be-stored data to the memory cell with the erased status;
an erasing unit, configured to perform an erasing operation to prepare for a next data writing operation after writing the to-be-stored data into the memory cell with the erased status;
a second acquisition unit, configured to obtain the identification information of each segment of the to-be-stored data respectively when two memory cells are at the valid state and have a same logic address; and
a second determining unit, configured to determine serial numbers of the two memory cells.

### Claim 10 (depends on 9)

The control apparatus according to claim 9, wherein:
the erasing unit is also configured to perform an erasing operation to a memory cell with a data status of the indefinite state to turn the memory cell with a data status of the indefinite state into a memory cell with a data state of the erased state when one memory cell of the targeted memory zone has a data status of the indefinite state and other memory cell of the targeted memory are at the valid state.

### Claim 11

A control apparatus of a memory including a targeted memory zone having a plurality of memory cells, a storage capacity of each memory cell being one page, the apparatus comprising:
a first acquisition unit, configured to receive a to-be-stored data and obtain a targeted address of the to-be-stored data;
a read out unit, configured to read out data status of all memory cells of the target memory zone;
a programming unit, configured to perform a programming operation to a memory cell with an erased status and write the to-be-stored data to the memory cell with the erased status; and
an erasing unit, configured to perform an erasing operation to prepare for a next data writing operation after writing the to-be-stored data into the memory cell with the erased status, wherein:
the erasing unit is also configured to perform an erasing operation to a memory cell having a larger serial number when the memory cell and another memory cell are both at the valid state and have a same logic address.

### Claim 12 (depends on 9)

The control apparatus according to claim 9, wherein the to-be-stored data comprises:
data information;
targeted address information; and
identification information of the data.

### Claim 13 (depends on 9)

The control apparatus according to claim 9, wherein:
the erasing unit is also configured to erase a memory cell with a larger serial number.

### Claim 14 (depends on 12)

The control apparatus according to claim 12, wherein the to-be-stored data further comprises:
determining information.

### Claim 15 (depends on 12)

The control apparatus according to claim 12, wherein:
the first determining unit is configured to obtain the determining information of the data in the memory cell corresponding to the targeted address according to the targeted address and determine if a data status of the memory cell corresponding to the targeted address is at the valid state according to the determining information.

### Claim 16 (depends on 9)

The control apparatus according to claim 9, wherein:
the memory is an electrically erasable programmable read-only memory (EEPROM).

### Claim 17 (depends on 1)

The memory control method according to claim 1, wherein the indefinite state is that the data in the memory cell is incomplete caused by an interruption of the erase operation performed on the memory cell or by an interruption of the programming operation performed on the memory cell.

### Claim 18 (depends on 11)

The control apparatus according to claim 11, wherein the to-be-stored data comprises:
data information;
targeted address information; and
identification information of the data.