# US 10,310,764 B2 · Semiconductor memory device and storage apparatus comprising semiconductor memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,310,764 B2
- Document ID: US10310764B2
- Status: Granted
- Kind: B2
- Application number: 15/518,289
- Filed: 2014-11-04
- Published: 2017-10-26
- Granted: 2019-06-04
- Earliest claimed: 2014-11-04
- Assignees: Hitachi, Ltd.
- Applicants: Hitachi, Ltd.
- Inventors: Akifumi Suzuki; Mitsuhiro Okada; Satoshi Morishita
- Web page: https://patentgrep.com/patent/US10310764B2

## CPC

- G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration}
- G06F 3/0611: {in relation to response time}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence)
- G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/16: Protection against loss of memory contents {(contains no material, see G06F11/00)}
- G06F 2212/1024: Latency reduction
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The semiconductor memory device comprises a memory element group (one or more semiconductor memory elements) and a memory controller. The memory controller comprises a processor configured to process at least a part of an I/O command from a higher-level apparatus when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a memory controller including a processor configured to process at least a part of an I/O (Input/Output) command from a higher-level apparatus when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits, which are different from the processor, and are configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition; and
a memory element group that is one or more semiconductor memory elements configured to store data input and output by the memory controller, the data being at least a part of I/O target data associated with the I/O command,
wherein the memory controller comprises a temporary memory area, and
wherein the predetermined condition is satisfied when at least a part of the I/O target data is stored in the temporary memory area.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the one or more hardware logic circuits include:
a command division unit that is a hardware logic circuit configured to divide the I/O command into a plurality of sub-I/O commands; and
a determination unit that is a hardware logic circuit configured to determine, for each of the sub-I/O commands, whether the sub-I/O target data associated with the sub-I/O command is stored in the temporary memory area or not, and
wherein the sub-I/O command(s) for which the corresponding sub-I/O target data is determined to be stored in the temporary memory area is processed by the processor.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein
the memory controller is configured to manage, for each of unit logical areas into which a logical space to be provided for the higher-level apparatus is divided to have a predetermined size, an association relationship between a logical address of the unit logical area and a physical address of the memory element group, and
the command division unit is configured to divide the I/O command into the sub-I/O commands for I/O of the sub-I/O target data having a size identical to the predetermined size.

### Claim 4 (depends on 2)

The semiconductor memory device according to claim 2, wherein
the memory element group includes a plurality of physical areas, and is configured to input and output data in units of the physical areas, and
the command division unit is configured to divide the I/O command into the sub-I/O commands for I/O of the sub-I/O target data having a size identical to a size of the physical area.

### Claim 5 (depends on 2)

The semiconductor memory device according to claim 2, wherein
the memory controller comprises a plurality of memory element interfaces,
a plurality of sub memory element groups are respectively coupled to the plurality of memory element interfaces,
each of the sub memory element groups is one or more memory elements,
the I/O command is a read command,
the plurality of sub-I/O commands are respectively a plurality of sub-read commands, and
the one or more hardware logic circuits include a command internal process unit that is a hardware logic circuit configured to activate in parallel two or more memory element interfaces so as to read two or more sub-read data respectively from the two or more physical areas in parallel, the memory element interfaces being respectively coupled to two or more physical areas respectively corresponding to two or more sub-read commands.

### Claim 6 (depends on 2)

The semiconductor memory device according to claim 2, wherein
the I/O command is a read command,
the plurality of sub-I/O commands are respectively a plurality of sub-read commands,
the one or more hardware logic circuits include a command internal process unit that is a hardware logic circuit configured to read sub-read data from a physical area corresponding to the registered sub-read command,
the processor is configured to perform another process that is a process that includes deleting or changing data in the temporary memory area in parallel to a process of the sub-read command, and updating an association relationship between a logical address and a physical address, and
the processor is configured to register the sub-read command corresponding to the sub-read data in the command internal process unit, when the sub-read data is determined to be stored in the temporary memory area and subsequently the sub-read data is determined to be absent in the temporary memory area.

### Claim 7 (depends on 2)

The semiconductor memory device according to claim 2, wherein
the I/O command is a write command,
the plurality of sub-I/O commands are respectively a plurality of sub-write commands,
the processor is configured to perform another process that is a process that includes deleting or changing data in the temporary memory area in parallel to a process of the sub-write command, and updating an association relationship between a logical address and a physical address, and
the processor is configured to release, from the temporary memory area, an area where previous sub-write data is stored, when a storage destination area of new sub-write data that is sub-write data associated with the sub-write command is reserved in the temporary memory area and the previous sub-write data is stored in the temporary memory area, the previous sub-write data being sub-write data to be updated with the new sub-write data.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein
a predetermined hardware logic circuit among the one or more hardware logic circuits is configured to notify the higher-level apparatus of completion of the write command, when the plurality of sub-read commands respectively corresponding to the sub-write commands are stored in the temporary memory area.

### Claim 9 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the temporary memory area is a buffer.

### Claim 10 (depends on 1)

The semiconductor memory device according to claim 1, wherein
each of the one or more hardware logic circuits is configured to output information that indicates a result of a process, to a log area, and
the processor is configured to identify at least one of a failure site and failure details from information stored in the log area, in case a failure occurs.

### Claim 11 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the memory element group includes a plurality of high-speed physical areas and a plurality of low-speed physical areas,
a logical space provided for the higher-level apparatus by the memory controller is divided into a high-speed logical area that is a logical area to which the high-speed physical area is allocated, and a low-speed logical area that is a logical area to which the low-speed physical area is allocated,
a process of an I/O command where a logical address belonging to the high-speed logical area is designated is performed by at least one among the one or more hardware logic circuits but not by the processor, and
a process of an I/O command where a logical address belonging to the low-speed logical area is designated is performed not only by at least one among the one or more hardware logic circuits but also by the processor.

### Claim 12 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the memory controller is configured to receive the I/O command according to PCI-Express from the higher-level apparatus.

### Claim 13

A storage apparatus, comprising:
a plurality of semiconductor memory devices; and
a storage controller configured to transmit an I/O command to at least one of the plurality of semiconductor memory devices, based on an I/O request issued by a host computer,
the at least one of the plurality of the semiconductor memory devices comprising:
a memory controller including a processor configured to process at least a part of the I/O command from the storage controller when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits, which are different from the processor, and are configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition; and
a memory element group that is one or more semiconductor memory elements configured to store data input and output by the memory controller, the data being at least a part of I/O target data associated with the I/O command,
wherein the memory controller comprises a temporary memory area, and
wherein the predetermined condition is satisfied when at least a part of the I/O target data is stored in the temporary memory area.