# US 10,310,743 B2 · Latency improvements between sub-blocks

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- Number: US 10,310,743 B2
- Document ID: US10310743B2
- Status: Granted
- Kind: B2
- Application number: 15/714,743
- Filed: 2017-09-25
- Published: 2019-03-28
- Granted: 2019-06-04
- Earliest claimed: 2017-09-25
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Parthasarathy Gajapathy
- Web page: https://patentgrep.com/patent/US10310743B2

## CPC

- G06F 3/0611: {in relation to response time}
- G06F 15/76: Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16)
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 15/00: Digital computers in general (details G06F1/00 – G06F13/00); Data processing equipment in general
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor device includes a first functional block. The first functional block includes one or more input buffers configured to receive signals, and one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block. The semiconductor device also includes a second functional block coupled to the first functional block. The second functional block includes a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block.

## Claims

### Claim 1

A semiconductor device, comprising:
a first functional block, comprising:
one or more input buffers configured to receive signals; and
one or more flip-flops configured to receive the signals from the one or more input buffers and output the received signals from the first functional block; and
a command decoder coupled to the first functional block, comprising:
a decode logic configured to directly receive the output signals from the one or more flip-flops of the first functional block; and
one or more flip-flops configured to receive decoded signals from the decode logic and output the decoded signals from the command decoder, wherein the one or more flip-flops of the first functional block and the one or more flip-flops of the command decoder receive identical clock signals.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first functional block comprises a command interface configured to receive the signals comprising command/address signals.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first functional block comprises a clock input circuit configured to send clock signals and the one or more flip-flops of the first functional block are latched based on the clock signals.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the one or more flip-flops of the command decoder are configured to be latched based on one or more clock signals.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a clock cycle period of the DDR5 SDRAM device is less than or equal to about 500 picoseconds.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the clock cycle period of the DDR5 SDRAM device is approximately 416 picoseconds.

### Claim 8

A semiconductor device, comprising:
a first functional block, comprising:
logic configured to receive signals; and
one or more flip-flops configured to latch the signals received by the logic and output the signals from the first functional block; and
a second functional block coupled to the first functional block, comprising a decode logic configured to receive the signals output from the one or more flip-flops of the first functional block, wherein the second functional block does not comprise flip-flops between the one or more flip-flops of the first functional block and the decode logic of the second functional block, and wherein the second functional block comprises one or more flip-flops configured to receive an output from the decode logic;
wherein the one or more flip-flops of the first functional block and the one or more flip-flops of the second functional block are configured to be latched by identical clock signals, wherein the second functional block is a command decoder.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first functional block comprises a command interface configured to receive and output command/address signals.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the logic comprise one or more input buffers.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first functional block comprises a clock input circuit configured to send the clock signals and the one or more flip-flops of the first functional block are latched based on the clock signals.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein one or more flip-flops of the second functional block coupled to the decode logic are configured to receive decoded signals from the decode logic and output the decoded signals from the second functional block.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the semiconductor device is a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device.