# US 10,310,740 B2 · Aligning memory access operations to a geometry of a storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,740 B2 - Document ID: US10310740B2 - Status: Granted - Kind: B2 - Application number: 14/748,194 - Filed: 2015-06-23 - Published: 2016-12-29 - Granted: 2019-06-04 - Earliest claimed: 2015-06-23 - Assignees: Pure Storage, Inc. - Applicants: Pure Storage, Inc. - Inventors: John Colgrove; Peter E. Kirkpatrick - Web page: https://patentgrep.com/patent/US10310740B2 ## CPC - G06F 3/061: {Improving I/O performance} - G06F 3/064: {Management of blocks} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Aligning memory access operations to a geometry of a storage device, including: receiving, by a storage array controller, information describing the layout of memory in the storage device; determining, by the storage array controller, a write size in dependence upon the layout of memory in the storage device; and sending, by the storage array controller, a write request addressed to a location within the memory unit in dependence upon the layout of memory in the storage device. ## Claims ### Claim 1 A method of aligning memory access operations to a geometry of a single storage device, the method comprising: receiving, by a storage array controller, information describing the layout of memory in the single storage device; determining, by the storage array controller, and in dependence upon the layout of memory in the single storage device, a write size and a physical address; and sending, by the storage array controller, a write request specifying the write size and addressed to the physical address within the single storage device. ### Claim 2 (depends on 1) The method of claim 1 further comprising sending, by the storage array controller, a request to expose an underlying physical layout of the memory in the storage device. ### Claim 3 (depends on 1) The method of claim 1 wherein the information describing the layout of memory in the single storage device includes information describing a size of a writeable memory unit in the storage device, and wherein the storage array controller, in dependence upon the storage array controller determining the physical address, relieves the single storage device from translating a logical address for the write request into the physical address. ### Claim 4 (depends on 1) The method of claim 1 wherein the information describing the layout of memory in the single storage device includes information describing a size of an erasable memory unit in the single storage device. ### Claim 5 (depends on 1) The method of claim 1 wherein sending, by the storage array controller, the write request specifying the write size and addressed to the the physical address within the single storage device further comprises: identifying an unused portion of the single storage device; and including an address for the unused portion of the single storage device in the write request. ### Claim 6 (depends on 3) The method of claim 3 wherein sending, by the storage array controller, the write request specifying the write size and addressed to the the physical address within the single storage device further comprises: identifying an unused memory unit of the single storage device; and including an address for the unused memory unit in the write request. ### Claim 7 A storage array controller for aligning memory access operations to a geometry of a single storage device, the storage array controller comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the storage array controller to perform operations comprising: receiving information describing the layout of memory in the single storage device; determining, in dependence upon the layout of memory in the single storage device, a write size and a physical address; and sending a write request specifying the write size and addressed to the physical address within the single storage device. ### Claim 8 (depends on 7) The storage array controller of claim 7 further comprising computer program instructions that, when executed by the computer processor, cause the storage array controller to perform operations comprising sending a request to expose an underlying physical layout of the memory in the single storage device. ### Claim 9 (depends on 7) The storage array controller of claim 7 wherein the information describing the layout of memory in the storage device includes information describing a size of a writeable memory unit in the single storage device. ### Claim 10 (depends on 7) The storage array controller of claim 7 wherein the information describing the layout of memory in the storage device includes information describing a size of an erasable memory unit in the single storage device. ### Claim 11 (depends on 9) The storage array controller of claim 9 wherein sending a write request addressed to the physical address within the single storage device further comprises: identifying an unused portion of the memory unit; and including an address for the unused portion of the memory unit in the write request. ### Claim 12 (depends on 9) The storage array controller of claim 9 wherein sending a write request addressed to the physical address within the single storage device further comprises: identifying an unused memory unit of the single storage device; and including an address for the unused memory unit in the write request. ### Claim 13 A computer program product for aligning memory access operations to a geometry of a single storage device, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a storage controller to perform operations comprising: receiving, by the storage array controller, information describing the layout of memory in the single storage device; determining, by the storage array controller, and in dependence upon the layout of memory in the single storage device, a write size and a physical address; and sending, by the storage array controller, a write request specifying the write size and addressed to the physical address within the single storage device. ### Claim 14 (depends on 13) The computer program product of claim 13 further comprising sending, by the storage array controller, a request to expose an underlying physical layout of the memory in the single storage device. ### Claim 15 (depends on 13) The computer program product of claim 13 wherein the information describing the layout of memory in the storage device includes information describing a size of a writeable memory unit in the single storage device. ### Claim 16 (depends on 13) The computer program product of claim 13 wherein the information describing the layout of memory in the storage device includes information describing a size of an erasable memory unit in the single storage device. ### Claim 17 (depends on 15) The computer program product of claim 15 wherein sending, by the storage array controller, the write request addressed to the physical address within the single storage further comprises: identifying an unused portion of the memory unit; and including an address for the unused portion of the memory unit in the write request. ### Claim 18 (depends on 15) The computer program product of claim 15 wherein sending, by the storage array controller, the write request addressed to the physical address within the single storage further comprises: identifying an unused memory unit; and including an address for the unused memory unit in the write request.