# US 10,310,735 B2 · Data storage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,735 B2 - Document ID: US10310735B2 - Status: Granted - Kind: B2 - Application number: 15/440,254 - Filed: 2017-02-23 - Published: 2017-08-31 - Granted: 2019-06-04 - Earliest claimed: 2016-02-25 - Assignees: Arm Limited - Applicants: ARM Limited - Inventors: Cédric Denis Robert Airaud; Max John Batley; Ian Michael Caulfield; Thomas Edward Roberts - Web page: https://patentgrep.com/patent/US10310735B2 ## CPC - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/061: {Improving I/O performance} - G06F 3/0638: {Organizing or formatting or addressing of data} - G06F 3/0673: {Single storage device} - G06F 12/0223: {User address space allocation, e.g. contiguous or non contiguous base addressing} - G06F 12/0646: {Configuration or reconfiguration} - G06F 12/0893: Caches characterised by their organisation or structure - G06F 2212/1016: Performance improvement - G06F 2212/1028: Power efficiency - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Data storage apparatus comprises detection circuitry configured to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator configured to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector configured to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry configured to control operation of the data storage apparatus in dependence upon the reference memory address when a match is detected by the detector. ## Claims ### Claim 1 Data storage apparatus comprising: detection circuitry to detect a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection circuitry comprising: a comparator to compare, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; the comparator being configured to compare, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; a detector to detect the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and control circuitry to control operation of the data storage apparatus in dependence upon the reference memory address when a match is detected by the detector. ### Claim 2 (depends on 1) Apparatus according to claim 1, in which: the first subset of bits comprises a contiguous set of less significant bits; and the second subset of bits comprises all remaining bits which are more significant than those bits in the first subset of bits. ### Claim 3 (depends on 1) Apparatus according to claim 1, comprising an abort detector to provide an abort indication to the control circuitry when a predetermined condition applies to one or more bits of the second subset of the address offset. ### Claim 4 (depends on 3) Apparatus according to claim 3, in which the controller is configured to cancel a data access by the data storage access in response to the abort indication. ### Claim 5 (depends on 3) Apparatus according to claim 3, in which the controller is configured, in response to the abort indication, to change a mode of operation for a data access by the data storage apparatus. ### Claim 6 (depends on 3) Apparatus according to claim 3, in which the combination is an addition. ### Claim 7 (depends on 6) Apparatus according to claim 6, in which the abort detector is configured to provide the abort indication to the control circuitry when a carry amount from the addition is different to a group of one or more bits of the second subset of the address offset. ### Claim 8 (depends on 1) Apparatus according to claim 1, comprising a first storage arrangement to store information relating to one or more recently-accessed data items in a second storage arrangement; and in which: the reference address is a memory address of one of the data items for which information is held in the first storage arrangement; and the test address is the address of a currently required data item. ### Claim 9 (depends on 8) Apparatus according to claim 8, in which the control circuitry is configured to selectively enable or disable access to the second storage arrangement in dependence upon whether a match is detected between the reference memory address and the test address. ### Claim 10 (depends on 9) Apparatus according to claim 9, in which the control circuitry is configured to disable access to the second storage arrangement when a match is detected between the reference memory address and the test address. ### Claim 11 (depends on 1) Apparatus according to claim 1, in which the reference memory address, the base address and the address offset each comprise the same number of bits. ### Claim 12 Data storage apparatus comprising: detection means for detecting a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detection means being configured to: means for comparing, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; means for comparing, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; means for detecting the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and means for controlling operation of the data storage apparatus in dependence upon the reference memory address when a match is detected. ### Claim 13 A method of data storage operation, the method comprising: detecting a match between a multi-bit reference memory address and a test address, the test address being a combination of a multi-bit base address and a multi-bit address offset, the detecting step comprising: comparing, as a first comparison, a first subset of bits of the reference memory address with a combination of the corresponding first subset of bits of the base address and the corresponding first subset of bits of the address offset; comparing, as a second comparison, a second, different subset of bits of the reference memory address with the corresponding second subset of bits of the base address; detecting the match between the reference memory address and the test address when both of the first comparison and the second comparison detect a respective match; and controlling operation of the data storage apparatus in dependence upon the reference memory address when a match is detected.