# US 10,310,586 B2 · Memory power savings in idle display case

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- Number: US 10,310,586 B2
- Document ID: US10310586B2
- Status: Granted
- Kind: B2
- Application number: 14/980,912
- Filed: 2015-12-28
- Published: 2016-04-28
- Granted: 2019-06-04
- Earliest claimed: 2013-05-09
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Sukalpa Biswas; Shinye Shiu; Cyril de la Cropte de Chanterac; Manu Gulati; Pulkit Desai; Rong Zhang Hu
- Web page: https://patentgrep.com/patent/US10310586B2

## CPC

- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3218: of display devices
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 3/14: Digital output to display device {; Cooperation and interconnection of the display device with other functional units}
- G06F 12/0873: Mapping of cache memory to specific storage devices or parts thereof
- G09G 5/001: {Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor}
- G09G 5/393: Arrangements for updating the contents of the bit-mapped memory
- G09G 5/395: Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence)
- G06F 2212/455: Image or video data
- G09G 2330/02: Details of power systems and of start or stop of display operation
- G09G 2330/021: Power management, e.g. power saving
- G09G 2360/121: using a cache memory
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

## Claims

### Claim 1

A method comprising:
in a system including a plurality of components coupled to a memory controller having a memory cache capable of entering a cache power down state, the memory controller controlling a memory responsive to memory operations from the plurality of components;
caching, in the memory cache, at least some memory data accessed from the memory responsive to the memory operations from the plurality of components, wherein the memory is not accessed and the memory cache is accessed for a given memory operation from a given component of the plurality of components in response to a hit for the given memory operation in the memory cache, wherein the plurality of components comprise one or more central processing unit (CPU) processors, and wherein a portion of the memory data cached in the memory cache is CPU data accessed by the one or more CPU processors;
detecting an idle screen for a display device in the system;
disabling the cache power down state in the memory cache responsive to detecting the idle screen;
disabling memory cache size reduction responsive to detecting the idle screen, whereby the memory cache remains full size responsive to disabling memory cache size reduction;
detecting an exit from the idle screen; and
enabling memory cache size reduction responsive to detecting the exit.

### Claim 2 (depends on 1)

The method as recited in claim 1 further comprising:
enabling caching of frame data in the memory cache responsive to detecting the idle screen, wherein caching of frame data is disabled during times that the idle screen is not detected.

### Claim 3 (depends on 1)

The method as recited in claim 1 wherein detecting the exit comprises detecting that at least one component of the plurality of components is to be powered on.

### Claim 4 (depends on 1)

The method as recited in claim 1 further comprising:
detecting an exit from the idle screen; and
enabling the cache power down state in the memory cache responsive to detecting the exit.

### Claim 5 (depends on 4)

The method as recited in claim 4 wherein detecting the exit comprises detecting that at least one component of the plurality of components is to be powered on.

### Claim 6 (depends on 4)

The method as recited in claim 4 wherein detecting the exit comprises detecting that a graphics device is requesting to be powered on.

### Claim 7 (depends on 4)

The method as recited in claim 4 further comprising:
filtering wake/sleep events for one or more processors in the system; and
detecting the exit from the idle screen responsive to the filtered wake/sleep events indicating that the processor is potentially active.

### Claim 8

An apparatus comprising:
a plurality of components;
a memory system coupled to the plurality of components;
a memory cache coupled to the memory system and configured to cache data accessed in the memory system by the plurality of components, wherein the memory cache is checked for a hit prior to accessing the memory system in response to a memory operation, wherein the memory system is not accessed and the memory cache is accessed in response to the hit for a memory operation, wherein the plurality of components comprise one or more central processing unit (CPU) processors, and wherein a portion of the memory data cached in the memory cache is CPU data accessed by the one or more CPU processors; and
a display controller coupled to the memory cache and the memory system, wherein the display controller is configured to generate memory operations to read at least one frame buffer stored in the memory system to display images on a display device, and wherein the memory cache is programmed during use to disable the memory cache from entering a power down state responsive to the images on the display device being static, and wherein the memory cache is programmed, during use, to disable memory cache automatic resizing responsive to the images on the display device being static, whereby the memory cache remains full size responsive to disabling of memory cache automatic resizing, and wherein the memory cache is programmed, during use, to enable memory cache automatic resizing responsive to the images displayed by the display controller being dynamic.

### Claim 9 (depends on 8)

The apparatus as recited in claim 8 wherein the display controller is programmable to request allocation in the memory cache for the frame buffer data when transmitting the memory operations, and wherein the display controller is programmed during use to request allocation in response to the images on the display device being static, and wherein the display controller is programmed during use not to request allocation in response to the images on the display device being dynamic.

### Claim 10 (depends on 8)

The apparatus as recited in claim 8 wherein the one or more CPU processors are configured to execute a plurality of instructions stored in the memory system during use, and wherein the plurality of instructions, when executed, detect the static images and dynamic images.

### Claim 11 (depends on 10)

The apparatus as recited in claim 10 further comprising a power manager circuit coupled to the plurality of components and the display controller, and wherein the plurality of instructions includes a plurality of drivers, each driver of the plurality of drivers corresponding to a respective one of the plurality of components, and wherein the plurality of instructions include a power manager driver corresponding to the power manager circuit, and wherein the plurality of drivers are configured to communicate power up and power down requests to the power manager driver for their respective components, and wherein the power manager driver is configured to detect the static images and the dynamic images responsive to the power up and power down requests.

### Claim 12 (depends on 8)

The apparatus as recited in claim 8 wherein the memory cache is programmed, during use, to enable cache power down responsive to the images being displayed by the display controller being dynamic.

### Claim 13

A non-transitory computer accessible storage medium storing a plurality of instructions executable by one or more processors in an integrated circuit that also includes a display controller, a memory controller that includes a memory cache, a plurality of components including one or more central processing unit (CPU) processors, and a power manager circuit, the plurality of instructions including:
a power manager driver corresponding to the power manager circuit;
a memory driver corresponding to the memory controller; and
a display driver corresponding to the display controller, wherein the display driver detects that images being displayed by the display controller are static, and wherein the memory driver disables a memory cache power down state responsive to the static images, and wherein the memory cache is configured to cache data read from memory by the plurality of components, including the one or more CPU processors, wherein the memory controller checks the memory cache for a hit for the memory operations from the plurality of components, and the memory controller does not access the memory and accesses the memory cache in response to the hit for a given memory operation, and wherein the memory driver disables memory cache automatic resizing responsive to the static images, whereby the memory cache remains full size responsive to disabling memory cache automatic resizing, and wherein the display driver detects that the images being displayed are dynamic, and wherein the memory driver enables the memory cache automatic resizing responsive to the dynamic images.

### Claim 14 (depends on 13)

The non-transitory computer accessible storage medium as recited in claim 13 wherein the display driver detects that the images being displayed are dynamic, and wherein the memory driver enables the memory cache power down state responsive to the dynamic images.