# US 10,310,549 B1 · Clock signal generating circuit and operating method thereof

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- Number: US 10,310,549 B1
- Document ID: US10310549B1
- Status: Granted
- Kind: B1
- Application number: 16/013,965
- Filed: 2018-06-21
- Granted: 2019-06-04
- Earliest claimed: 2018-06-21
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Chuan-Jen Chang; Wen-Ming Lee
- Web page: https://patentgrep.com/patent/US10310549B1

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413)
- H03K 5/00006: {Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68)}
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

## Claims

### Claim 1

An operating method of a clock signal generating circuit, comprising:
transmitting a clock signal to a clock tree circuit by a voltage detector; and
adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

### Claim 2 (depends on 1)

The operating method of claim 1, further comprising:
increasing the frequency of the clock signal when the voltage is higher than a voltage upper threshold; and
decreasing the frequency of the clock signal when the voltage is lower than a voltage lower threshold.

### Claim 3 (depends on 1)

The operating method of claim 1, wherein the voltage is an operating voltage of the clock tree circuit.

### Claim 4 (depends on 1)

The operating method of claim 1, further comprising:
generating the clock signal by a signal generating circuit.

### Claim 5 (depends on 1)

The operating method of claim 1, further comprising:
detecting the voltage of the clock tree circuit by the voltage detector.

### Claim 6

A clock signal generating circuit, comprising:
a clock tree circuit; and
a voltage detector, coupled to the clock tree circuit, wherein the voltage detector is configured to transmit a clock signal to the clock tree circuit;
wherein the voltage detector adjusts a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

### Claim 7 (depends on 6)

The clock signal generating circuit of claim 6, wherein the voltage detector is further configured to increase the frequency of the clock signal when the voltage is higher than a voltage upper threshold, and the voltage detector is configured to decrease the frequency of the clock signal when the voltage is lower than a voltage lower threshold.

### Claim 8 (depends on 6)

The clock signal generating circuit of claim 6, wherein the voltage is an operating voltage of the clock tree circuit.

### Claim 9 (depends on 6)

The clock signal generating circuit of claim 6, wherein the voltage detector comprises:
a signal generating circuit, configured to generate the clock signal.

### Claim 10 (depends on 6)

The clock signal generating circuit of claim 6, wherein the voltage detector is further configured to detect the voltage of the clock tree circuit.