# US 10,310,548 B2 · Expected lifetime management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,548 B2 - Document ID: US10310548B2 - Status: Granted - Kind: B2 - Application number: 15/345,228 - Filed: 2016-11-07 - Published: 2018-05-10 - Granted: 2019-06-04 - Earliest claimed: 2016-11-07 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Hee jun Park; Robert Allen Shearer; Victorya Vishnyakov - Web page: https://patentgrep.com/patent/US10310548B2 ## CPC - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 9/44521: {Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading} - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 11/3058: {Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206)} - G06F 11/3433: {for load management (allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029)} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G01R 31/287: {Procedures; Software aspects} - G06F 11/008: {Reliability or availability analysis} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A circuit block is operated, for limited times, at a boosted frequency that is above the conventional maximum operating frequency specified to achieve an expected lifetime goal. The aging caused by both regular operation and boosted frequency operation is estimated and tracked block-by-block over the both the lifetime of the part and over shorter windows of time (e.g., daily, weekly, monthly, etc.) The shorter time windows are dynamically assigned aging budgets to ensure the part will still be expected to meet the expected lifetime even though its aging will be at an ‘accelerated’ rate whenever the block is operated at a boosted frequency. Aging budgets are assigned based on estimates of the amount of aging the block has experienced, and the amount of aging budget that is left for that time window. ## Claims ### Claim 1 An integrated circuit, comprising: a plurality of electronic components organized as at least two subsystem units, the at least two subsystem units including a first subsystem unit, the first subsystem unit associated with a first expected lifetime that is based at least in part on a conventional maximum operating frequency; and a clock manager configured to: determine, for each of a plurality of time windows, a respective aging estimate of the first subsystem unit; accumulate each respective aging estimate to thereby determine a first accumulated age estimate; and based on one or more of a first aging budget over a first moving time window and on the first accumulated age estimate, selectively operate the first subsystem unit at a boosted frequency that effects higher performance than the conventional maximum operating frequency, the first moving time window corresponding to a selected time interval that is less than the first expected lifetime. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the first aging budget is based at least in part on a predetermined amount of aging to be allowed over the selected time interval. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the first subsystem unit may be operated at the boosted frequency based at least in part on a first aging estimate being less than the predetermined amount of aging over the selected time interval. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the first subsystem unit may be operated at the boosted frequency based at least in part on the first accumulated age estimate being less than a maximum allowed aging versus elapsed time curve that is based at least in part on a linear interpolation of the first expected lifetime. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the clock manager is configured to, based at least in part on a second aging budget over a second moving time window, selectively operate a second subsystem unit at the boosted frequency, the second moving time window corresponding to the selected time interval. ### Claim 6 (depends on 5) The integrated circuit of claim 5, wherein the first subsystem unit is selected to be operated at the boosted frequency based at least in part on a first aging estimate being less of the first aging budget over the first moving time window than a second aging estimate is of the second aging budget over the second moving time window. ### Claim 7 A method of operating an integrated circuit that includes a plurality of electronic components organized as at least two subsystem units, comprising: monitoring a plurality of operating conditions of the at least two subsystem units; estimating a respective aging rate over a predetermined time period for each respective subsystem unit; accumulating, for each subsystem unit, a plurality of respective aging rates over a plurality of the predetermined time periods to determine a respective age of each respective subsystem unit; and based at least in part on the age of a respective subsystem unit, determining whether to allow that respective subsystem unit to be operated in a boosted frequency range that is greater than a conventional maximum operating frequency associated with an expected lifetime for the integrated circuit. ### Claim 8 (depends on 7) The method of claim 7, further comprising: based at least in part on the age of a respective subsystem unit, increasing a task allocation affinity corresponding to the respective subsystem unit in order to increase a probability the respective subsystem unit will be allocated a heavier workload. ### Claim 9 (depends on 7) The method of claim 7, further comprising: based at least in part on the age of a respective subsystem unit, decreasing a task allocation affinity corresponding to the respective subsystem unit in order to decrease a probability the respective subsystem unit will be allocated a heavier workload. ### Claim 10 (depends on 7) The method of claim 7, wherein the determination of whether to allow the respective subsystem unit to be operated in the boosted frequency range if further based at least in part on a respective aging rate of a predetermined time period. ### Claim 11 (depends on 10) The method of claim 10, wherein the respective aging rate is associated with the most recent predetermined time period. ### Claim 12 (depends on 7) The method of claim 7, wherein the determination of whether to allow the respective subsystem unit to be operated the boosted frequency range is further based at least in part on a temperature of the respective subsystem unit. ### Claim 13 (depends on 7) The method of claim 7, further comprising: based at least in part on determining that a task running on a subsystem unit that is operating in the boosted frequency range has exceeded a threshold amount of time to complete, stopping that subsystem unit from being operated in the boosted frequency range. ### Claim 14 (depends on 13) The method of claim 13, wherein after the task stops running on the subsystem unit, the subsystem unit is re-allowed to be operated in the boosted frequency range. ### Claim 15 A method of operating a plurality of processor cores on an integrated circuit, comprising: operating, for a first amount of time, a first processor core in a predetermined frequency range associated with an expected lifetime; operating, for a second amount of time, the first processor core in a boosted frequency range that has higher performance than the predetermined frequency range; calculating a first aging rate of the first processor core over a first time window based on the first amount of time; calculating a second aging rate of the processor core over a second time window based on the second amount of time; estimating an accumulated age of the first processor core by accumulating the first aging rate and the second aging rate; and based at least in part on the first amount of time and the second amount of time, determining whether to allow the first processor core to operate in the boosted frequency range. ### Claim 16 (depends on 15) The method of claim 15, wherein the determination of whether to allow the first processor core to operate in the boosted frequency range is based at least in part on the first aging rate and the second aging rate. ### Claim 17 (depends on 15) The method of claim 15, wherein the determination of whether to allow the first processor core to operate in the boosted frequency range is based at least in part on the accumulated age of the first processor core meeting a threshold criteria. ### Claim 18 (depends on 17) The method of claim 17, wherein the threshold criteria is based at least in part on a linear interpolation of the expected lifetime. ### Claim 19 (depends on 18) The method of claim 18, further comprising: based at least in part on the first aging rate over the first time window and an aging rate of a second processor core over the first time window, adjusting a first task allocation affinity associated with the first processor core relative to a second task allocation affinity associated with the second processor core.