# US 10,310,490 B2 · Method and apparatus of evaluating a semiconductor manufacturing process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,490 B2 - Document ID: US10310490B2 - Status: Granted - Kind: B2 - Application number: 15/011,962 - Filed: 2016-02-01 - Published: 2017-08-03 - Granted: 2019-06-04 - Earliest claimed: 2016-02-01 - Assignees: Qoniac GmbH - Applicants: Qoniac GmbH - Inventors: Stefan Buhl; Martin Rößiger; Boris Habets - Web page: https://patentgrep.com/patent/US10310490B2 ## CPC - G05B 19/418: Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] - G05B 19/4184: {characterised by fault tolerance, reliability of production system} - H10P 72/0612: {Production flow monitoring, e.g. for increasing throughput} - H10P 74/238: {comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement} - G05B 2219/45031: Manufacturing semiconductor wafers - Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A method and apparatus for evaluating and controlling a semiconductor manufacturing process having a plurality of process steps in a process flow is described. The method comprises retrieving measurements of process step parameters from a process measurement database. The process step parameters comprise at least one of process step measurement data, process step context data or process step control data. The process step parameters are subsequently associated with one or more of the process steps. ## Claims ### Claim 1 A method of evaluating and controlling a semiconductor manufacturing process of a semiconductor wafer comprising at least one layer, the semiconductor manufacturing process having a plurality of process steps in a process flow, the method comprising: gathering process step parameters during or after any one of a plurality of process steps in a process flow of a semiconductor manufacturing process of a semiconductor wafer, during which at least one layer of the semiconductor wafer is processed, wherein the process step parameters comprise at least one of process step measurement data from measurements carried out on the semiconductor wafer, process step context data relating to the process steps, and comprising at least a layer name of the at least one layer, process step control data relating to processing tools used in the semiconductor manufacturing process, and post-process data derived from the process step measurement data based on a process model; associating the process step parameters, and thereby at least the layer name of the at least one layer, to one or more of the plurality of the process steps in the process flow; evaluating the semiconductor manufacturing process based on the process step parameters, wherein the evaluating comprises identifying at least one of the plurality of process steps and the associated layer name of the at least one layer; and reworking, dependent on a result of the evaluating, the at least one layer of the semiconductor wafer, and/or modifying the process step control data. ### Claim 2 (depends on 1) The method of claim 1, wherein the process step measurement data comprises at least one of an alignment measurement, an overlay measurement, a levelling measurement, an exposure dose, a critical dimension measurement, an etching measurement or a deposition measurement. ### Claim 3 (depends on 1) The method of claim 1, wherein the process step context data further comprises at least one of a lot identifier, wafer identifier, exposure date, exposure recipe, type of resist and developer, including batch number, process chamber identifier, a processing tool identifier, processing time, semiconductor wafer identifier, recipe name or type, reticle identifier, product or technology name, resist name, resist batch identifier, developer name, developer batch identifier, hot plate identifier, development chamber, rinse fluid name or data file name. ### Claim 4 (depends on 1) The method of claim 1, wherein the process step control data comprises at least one of process recipe steering parameters, target parameters including exposure dose, reference corrections, field fine correction, wafer grid corrections, focus corrections, exposure corrections, etch time, deposition time, gas flow rate and sputtering voltage. ### Claim 5 (depends on 1) The method of claim 1, further comprising deriving further parameters from the associated process step parameters. ### Claim 6 (depends on 1) The method of claim 1, wherein the association of the process step parameters with the one or more process steps is carried out based on process context parameters. ### Claim 7 (depends on 1) The method of claim 1, further comprising applying at least one of a feed forward correction or a feedback modification to at least one of the process step control data based on the evaluation. ### Claim 8 (depends on 1) The method of claim 1, further comprising applying a process model to the associated process step parameters and the process steps. ### Claim 9 (depends on 1) Use of the method of claim 1 for evaluation of at least one of excursion detection, significance analysis, in direct overlay measurement or evaluation of edge placement errors. ### Claim 10 A semiconductor fabrication assembly for a semiconductor manufacturing process of a semiconductor wafer comprising at least one layer, the semiconductor manufacturing process having a plurality of process steps, the semiconductor fabrication assembly comprising: an exposure tool; a developing unit; at least one of an etch chamber or a deposition chamber; a processor; and a process step measurement database collecting process parameters from at least one of the exposure tool, the developing unit, the deposition chamber and the etch chamber during or after any one of a plurality of process steps in a process flow of a semiconductor manufacturing process of a semiconductor wafer; wherein the processor in operation retrieves process step parameters from the process step measurement database, the process step parameters comprising at least one of process step measurement data from measurements carried out on the semiconductor wafer, post-process data derived from the process step measurement data based on a process model, process step context data relating to the process steps and comprising a layer name of the at least one layer, or process step control data relating to processing tools used in the semiconductor manufacturing process; associates the process step parameters, and thereby at least the layer name of the at least one layer, with one or more of the plurality of the process steps in the process flow; evaluates the semiconductor manufacturing process based on the process step parameters, wherein the evaluating comprises identifying at least one of the plurality of process steps and the associated layer name of the at least one layer, and controls, dependent on a result of the evaluation, reworking of at least one layer of the semiconductor wafer and/or modifying the process step control data associated to the identified at least one of the plurality of process steps.