# US 10,310,476 B2 · Using linked-lists to create feature rich finite-state machines in integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,476 B2 - Document ID: US10310476B2 - Status: Granted - Kind: B2 - Application number: 15/958,871 - Filed: 2018-04-20 - Published: 2018-11-01 - Granted: 2019-06-04 - Earliest claimed: 2017-04-26 - Assignees: Analog Devices Global Unlimited Company - Applicants: Analog Devices Global Unlimited Company - Inventors: Navdeep Singh Dhanjal; Shengbing Zhou - Web page: https://patentgrep.com/patent/US10310476B2 ## CPC - G05B 19/045: using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers - G06F 1/3296: by lowering the supply or operating voltage - G06F 12/0824: {Distributed directories, e.g. linked lists of caches} - H03K 19/0002: {Multistate logic (H03K19/02 takes precedence)} - G05B 2219/23289: State logic control, finite state, tasks, machine, fsm - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state. ## Claims ### Claim 1 A logic sequencer comprising: an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the hierarchical linked lists include one or more pointers to identify one or more control words in the hierarchical linked lists associated with an IC state, and the sequencer circuitry is configured to: receive the one or more control words from the hierarchical linked lists; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state. ### Claim 2 (depends on 1) The logic sequencer of claim 1, wherein the hierarchical linked lists include a states list and an actions list, wherein the states list includes the available IC states and the actions list includes state actions performable by the IC, and wherein the states list includes an actions list pointer that identifies state actions of the actions list associated with a particular IC state. ### Claim 3 (depends on 2) The logic sequencer of claim 2, wherein the hierarchical linked lists include a rules list, wherein the actions list includes a rules list pointer and entries of the rules list identify one or more logic conditions associated with a state action of the actions lists. ### Claim 4 (depends on 3) The logic sequencer of claim 3, wherein the sequencer circuitry includes logic circuitry configured to implement the one or more logic conditions included in the rules list and advance the actions list pointer according to an outcome of the one or more logic conditions. ### Claim 5 (depends on 2) The logic sequencer of claim 2, wherein the hierarchical linked lists include a sequencer list that includes available IC state sequences and a states list pointer, wherein the states list pointer identifies the IC state of a current IC state sequence in the states list. ### Claim 6 (depends on 1) The logic sequencer of claim 1, wherein the sequencer circuitry is included in a power supply sequencer configured to activate a plurality of power supplies in a sequence determined according to a sequence of the IC states specified by the hierarchical linked lists. ### Claim 7 (depends on 1) The logic sequencer of claim 1, wherein the sequencer circuitry is included in a power supply sequencer configured to activate a plurality of voltage domains of an electronic system provided by the power supplies according to the sequence of IC states. ### Claim 8 A power supply management system, the system comprising: a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; an integrated circuit including sequencer circuitry electrically coupled to the plurality of power supplies; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine including a plurality of finite IC states; wherein the hierarchical linked lists include one or more pointers to identify one or more control words in the hierarchical linked lists associated with an IC state, and the sequencer circuitry is configured to: receive the one or more control words from the hierarchical linked lists; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state to coordinate activation and deactivation of the power supplies. ### Claim 9 (depends on 8) The system of claim 8, wherein the hierarchical linked lists include a states list and an actions list, wherein the states list includes the available IC states and the actions list includes state actions performable by the IC, and wherein the states list includes an actions list pointer that identifies state actions of the actions list corresponding to a particular IC state. ### Claim 10 (depends on 9) The system of claim 9, wherein the IC states included in the states list include fault states for one or more of the power supplies, and the actions list include actions performable by the IC when the IC state includes a fault state. ### Claim 11 (depends on 9) The system of claim 9, wherein the hierarchical linked lists include a rules list, wherein the actions list includes a rules list pointer and entries of the rules list identify one or more logic conditions associated with a state action of the actions lists. ### Claim 12 (depends on 11) The system of claim 11, wherein the sequencer circuitry includes logic circuitry configured to implement the one or more logic conditions included in the rules list and advance the actions list pointer according to an outcome of the one or more logic conditions. ### Claim 13 (depends on 9) The system of claim 9; wherein the hierarchical linked lists include a sequencer list that includes available IC state sequences and a states list pointer, wherein the states list pointer identifies the IC state of a current IC state sequence in the states list. ### Claim 14 (depends on 13) The system of claim 13, wherein the sequencer list includes a first state sequence to activate a first set of power supplies of the plurality of power supplies according to IC states of the first state sequence, and a second state sequence to activate a second set of power supplies of the plurality of power supplies according to IC states of the second state sequence. ### Claim 15 (depends on 8) The system of claim 8, wherein the sequencer circuitry is configured to activate a plurality of voltage domains of the system provided by the power supplies according to the control words corresponding to the IC states of the hierarchical linked lists. ### Claim 16 A non-transitory computer readable storage medium including instructions that, when performed by processing circuitry of a computing device, cause the computing device to perform acts comprising: implementing a graphical user interface (GUI) on the computing device; receiving power supply voltage sequencer information via the GUI; and configuring, using the power supply voltage sequencer information, a finite state machine as a plurality of hierarchical linked lists stored in a memory, wherein the finite state machine includes a plurality of device states of a power sequencer device that determine an order of activation of a plurality of power supplies, and the hierarchical linked lists include one or more pointers to identify, one or more control words in the hierarchical linked lists associated with the device states. ### Claim 17 (depends on 16) The non-transitory computer readable storage medium of claim 16, including instructions that cause the processing circuitry to generate the one or more control words stored in the memory and indexed according to the one or more pointers of the hierarchical linked lists; wherein the one or more control words correspond to an action performed by the power sequencer device when in a specified device state of the finite state machine. ### Claim 18 (depends on 16) The non-transitory computer readable storage medium of claim 16, including instructions that cause the processing circuitry to configure the hierarchical linked lists to include a states list and an actions list, wherein the states list includes the available device states and the actions list includes state actions performable by the device, and wherein the states list includes an actions list pointer that identifies state actions of the actions list corresponding to a particular device state. ### Claim 19 (depends on 18) The non-transitory computer readable storage medium of claim 18, including instructions that cause the processing circuitry to configure the hierarchical linked lists to include a rules list, wherein the actions list includes a rules list pointer and entries of the rules list identify one or more logic conditions associated with a state action of the actions lists. ### Claim 20 (depends on 16) The non-transitory computer readable storage medium of claim 16, including instructions that cause the processing circuitry to configure the finite state machine in one or more power supply sequencer devices, wherein a power supply sequencer device sequentially activates and deactivates power supplies to which it is connected according to the configured finite state machine.