# US 10,310,338 B2 · Manufacture method of IPS TFT-LCD array substrate and IPS TFT-LCD array substrate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,310,338 B2
- Document ID: US10310338B2
- Status: Granted
- Kind: B2
- Application number: 15/026,253
- Filed: 2016-02-25
- Published: 2018-03-01
- Granted: 2019-06-04
- Earliest claimed: 2016-01-11
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Xiangyang Xu
- Web page: https://patentgrep.com/patent/US10310338B2

## CPC

- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/0312: {characterised by the gate electrodes}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6743: {Silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/01: Manufacture or treatment
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3454: {Amorphous}
- H10P 14/44: Physical vapour deposition [PVD]
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 50/667: {by liquid etching only}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/2041: {Photolithographic processes}
- G02F 1/134318: {having a patterned common electrode}
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G02F 2201/121: common or background
- G02F 2201/122: having a particular pattern
- G02F 2201/123: pixel
- G02F 2202/103: a-Si
- H10D 30/674: {characterised by the active materials}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a manufacture method of an IPS TFT-LCD array substrate and an IPS TFT-LCD array substrate. In the manufacture method of the IPS TFT-LCD array substrate, the common electrode line and the gate are manufactured with the same metal layer, and the pixel electrode and the drain are manufactured with the same metal layer, and the via is formed in the insulation protective layer and the gate isolation layer correspondingly above the common electrode line; in the TFT array substrate, the pixel electrode and the drain are manufactured with the same metal layer, and the common electrode line and the gate are manufactured with the same metal layer, and the common electrode is transparent conductive material and located on the insulation protective layer, and the common electrode contact with the common electrode line through the via in the insulation protective layer and the gate isolation layer.

## Claims

### Claim 1

A manufacture method of an in-plane switching thin film transistor liquid crystal display (IPS TFT-LCD) array substrate, comprising steps of:
step 1, providing a substrate, and depositing a gate metal layer on the substrate, and patterning the gate metal layer to obtain a gate, a common electrode line and a gate scan line;
step 2, depositing a gate isolation layer on the gate metal layer, and depositing an amorphous silicon layer on the gate isolation layer, and patterning the amorphous silicon layer after performing N-type doping to the amorphous silicon layer to obtain a semiconductor layer correspondingly above the gate;
step 3, depositing a source-drain metal layer on the semiconductor layer and the gate isolation layer, and patterning the source-drain metal layer to obtain a source, a drain, a pixel electrode and a data line, and the source and the drain respectively contact with two ends of the semiconductor layer;
step 4, depositing an insulation protective layer on the source-drain metal layer, and patterning the insulation protective layer and the gate isolation layer to form a via correspondingly above the common electrode line in the insulation protective layer and the gate isolation layer;
step 5, depositing a transparent conductive layer on the insulation protective layer, and patterning the transparent conductive layer to obtain a common electrode, and the common electrode contacts with the common electrode line through the via;
wherein forming the pixel electrode is carried out posterior to forming the common electrode such that the common electrode is located above and isolated from the pixel electrode, the common electrode being spaced from the substrate by a distance greater than a distance by which the pixel electrode is spaced from the substrate.

### Claim 2 (depends on 1)

The manufacture method of the IPS TFT-LCD array substrate according to claim 1, wherein the gate metal layer is deposited by physical vapor deposition in the step 1, and a film thickness of the deposited gate metal layer is 3000-6000 Å, and material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the step of patterning the gate metal layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.

### Claim 3 (depends on 1)

The manufacture method of the IPS TFT-LCD array substrate according to claim 1, wherein the gate isolation layer and the amorphous silicon layer are deposited by chemical vapor deposition in the step 2, and a film thickness of the deposited gate isolation layer is 2000-5000 Å, and a film thickness of the deposited amorphous silicon layer is 1500-3000 Å, and the gate isolation layer is a silicon nitride layer, and the step of patterning the amorphous silicon layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.

### Claim 4 (depends on 1)

The manufacture method of the IPS TFT-LCD array substrate according to claim 1, wherein the source-drain metal layer is deposited by physical vapor deposition in the step 3, and a film thickness of the deposited gate metal layer is 3000-6000 Å, and material of the source-drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the step of patterning the source-drain metal layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.

### Claim 5 (depends on 1)

The manufacture method of the IPS TFT-LCD array substrate according to claim 1, wherein the insulation protective layer is deposited by chemical vapor deposition in the step 4, and a film thickness of the deposited insulation protective layer is 2000-5000 Å, and the insulation protective layer is a silicon nitride layer, and the step of patterning the insulation protective layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.

### Claim 6 (depends on 1)

The manufacture method of the IPS TFT-LCD array substrate according to claim 1, wherein the transparent conductive layer is deposited by physical vapor deposition in the step 5, and a film thickness of the deposited transparent conductive layer is 400-1000 Å, and material of the transparent conductive layer is one or more of Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide, Indium Germanium Zinc Oxide; the step of patterning the transparent conductive layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.

### Claim 7

An in-plane switching thin film transistor liquid crystal display (IPS TFT-LCD) array substrate, comprising a substrate, a plurality of gate scan lines, a plurality of data lines, a plurality of common electrode lines and a plurality of pixel units, divided by the plurality of gate scan lines and the plurality of data lines which are mutually insulated and staggered, and aligned in an array;
wherein each pixel unit comprises: a gate formed on the substrate, a gate isolation layer formed on the gate and the substrate, a semiconductor layer correspondingly above the gate and formed on the gate isolation layer, a source, a drain and a pixel electrode formed on the semiconductor layer and the gate isolation layer, an insulation protective layer formed on the source, the drain, the pixel electrode, the semiconductor layer and the gate isolation layer, and a common electrode formed on the insulation protective layer;
the pixel electrode, the source, the drain and the data lines are obtained after patterning a source-drain metal layer, and the common electrode lines, the gate and the gate scan lines are obtained after patterning a gate metal layer;
a via is provided in the insulation protective layer and the gate isolation layer correspondingly above the common electrode line, and the common electrode contacts with the common electrode line through the via;
the source and the drain respectively contact with two ends of the semiconductor layer;
wherein the common electrode is located above and isolated from the pixel electrode, the common electrode being spaced from the substrate by a distance greater than a distance by which the pixel electrode is spaced from the substrate.

### Claim 8 (depends on 7)

The IPS TFT-LCD array substrate according to claim 7, wherein material of the common electrode is transparent conductive material, and material of the transparent conductive material is one or more of Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide, Indium Germanium Zinc Oxide; a film thickness of the common electrode is 400-1000 Å.

### Claim 9 (depends on 7)

The IPS TFT-LCD array substrate according to claim 7, wherein material of the source-drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper, and a film thickness of the source-drain metal layer is 3000-6000 Å.

### Claim 10

A manufacture method of an in-plane switching thin film transistor liquid crystal display (IPS TFT-LCD) array substrate, comprising steps of:
step 1, providing a substrate, and depositing a gate metal layer on the substrate, and patterning the gate metal layer to obtain a gate, a common electrode line and a gate scan line;
step 2, depositing a gate isolation layer on the gate metal layer, and depositing an amorphous silicon layer on the gate isolation layer, and patterning the amorphous silicon layer after performing N-type doping to the amorphous silicon layer to obtain a semiconductor layer correspondingly above the gate;
step 3, depositing a source-drain metal layer on the semiconductor layer and the gate isolation layer, and patterning the source-drain metal layer to obtain a source, a drain, a pixel electrode and a data line, and the source and the drain respectively contact with two ends of the semiconductor layer;
step 4, depositing an insulation protective layer on the source-drain metal layer, and patterning the insulation protective layer and the gate isolation layer to form a via correspondingly above the common electrode line in the insulation protective layer and the gate isolation layer;
step 5, depositing a transparent conductive layer on the insulation protective layer, and patterning the transparent conductive layer to obtain a common electrode, and the common electrode contacts with the common electrode line through the via;
wherein forming the pixel electrode is carried out posterior to forming the common electrode such that the common electrode is located above and isolated from the pixel electrode, the common electrode being spaced from the substrate by a distance greater than a distance by which the pixel electrode is spaced from the substrate;
wherein the gate metal layer is deposited by physical vapor deposition in the step 1, and a film thickness of the deposited gate metal layer is 3000-6000 Å, and material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the step of patterning the gate metal layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
wherein the gate isolation layer and the amorphous silicon layer are deposited by chemical vapor deposition in the step 2, and a film thickness of the deposited gate isolation layer is 2000-5000 Å, and a film thickness of the deposited amorphous silicon layer is 1500-3000 Å, and the gate isolation layer is a silicon nitride layer, and the step of patterning the amorphous silicon layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
wherein the source-drain metal layer is deposited by physical vapor deposition in the step 3, and a film thickness of the deposited gate metal layer is 3000-6000 Å, and material of the source-drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper; the step of patterning the source-drain metal layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
wherein the insulation protective layer is deposited by chemical vapor deposition in the step 4, and a film thickness of the deposited insulation protective layer is 2000-5000 Å, and the insulation protective layer is a silicon nitride layer, and the step of patterning the insulation protective layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
wherein the transparent conductive layer is deposited by physical vapor deposition in the step 5, and a film thickness of the deposited transparent conductive layer is 400-1000 Å, and material of the transparent conductive layer is one or more of Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide, Indium Germanium Zinc Oxide; the step of patterning the transparent conductive layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.