# US 10,310,013 B2 · Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,310,013 B2
- Document ID: US10310013B2
- Status: Granted
- Kind: B2
- Application number: 15/470,880
- Filed: 2017-03-27
- Published: 2018-06-14
- Granted: 2019-06-04
- Earliest claimed: 2016-12-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Guangyuan Kelvin Ge; Rajesh Kashyap
- Web page: https://patentgrep.com/patent/US10310013B2

## CPC

- G01R 31/31721: {Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575)}
- G01R 31/31701: {Arrangements for setting the Unit Under Test [UUT] in a test mode}
- G01R 31/318508: {Board Level Test, e.g. P1500 Standard (features related to boundary scan G01R31/318533)}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Embodiments include a power isolation circuit. The power isolation circuit includes a logic block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The power control unit is coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and control the isolation cell dependent on the DFT internal core test mode control signal and the clamp control signal. Also disclosed is a multi-power domain multi-power isolation system, which includes a first power domain and a second power domain. The first power domain includes a logic block, wrapper cells, isolation cells, and a power control unit. The second power domain includes a logic block, wrapper cells, and level-shifter cells. The power control unit is coupled to the isolation cells. Additional power domains with similar characteristics can be included in the design.

## Claims

### Claim 1

An apparatus, comprising:
a logic block;
a wrapper cell coupled to the logic block;
an isolation cell coupled to the wrapper cell; and
a power control unit coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and to control the isolation cell based, at least in part, upon the DFT internal core test mode control signal and the clamp control signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the power control unit is configured to place the isolation cell into an internal core test mode dependent on the DFT internal core test mode control signal.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the power control unit comprises a logic gate, wherein the logic gate comprises:
a first input terminal to receive the DFT internal core test mode control signal;
a second input terminal to receive the clamp control signal; and
an output terminal configured to transmit a DFT clamp control signal to the isolation cell.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the logic gate is an OR gate.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein the isolation cell comprises a logic gate configured to receive the DFT clamp control signal from the power control unit.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the logic gate of the isolation cell is an OR gate comprising a first input terminal that is coupled to the wrapper cell, and a second input terminal that is configured to receive the DFT clamp control signal from the power control unit.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein:
the logic gate of the isolation cell is an AND gate having a first input terminal and a second input terminal;
the first input terminal of the AND gate is coupled to the wrapper cell;
the isolation cell further comprises an inverter coupled to the second input terminal of the AND gate; and
the inverter is configured to receive and invert the DFT clamp control signal.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein:
the inverter is referred to as a first inverter;
the apparatus further comprises a second isolation cell that comprises a second inverter coupled to the first inverter, and a second logic gate; and
wherein the second inverter is coupled to a first input terminal of the second logic gate.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the wrapper cell comprises:
a first selector;
a latch coupled to the first selector; and
a second selector coupled to the latch.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
the first selector is a first multiplexor;
the second selector is a second multiplexor; and
the latch is a clocked flip-flop.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein:
the first multiplexor comprises a first input terminal coupled to an output terminal of the logic block, and a second input terminal coupled to an output terminal of the clocked flip-flop;
the first multiplexor is controlled by a first control signal;
the second multiplexor comprises a first input terminal coupled to an output terminal of the first multiplexor, and a second input terminal that is configured to receive a scan path signal;
the second multiplexor is controlled by a second control signal; and
an output terminal of the second multiplexor is coupled to an input terminal of the clocked flip-flop.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the output terminal of the first multiplexor is coupled to the isolation cell.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein:
the isolation cell is referred to as a first isolation cell;
the wrapper cell is referred to as a first wrapper cell;
the apparatus further comprises a second isolation cell and a second wrapper cell;
an output terminal of the power control unit is coupled to the first and second isolation cells, and configured to transmit a DFT clamp control signal to the first and second isolation cells; and
the output terminal of the clocked flip-flop of the first wrapper cell is coupled to the second wrapper cell.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the second wrapper cell comprises:
a first multiplexor;
a clocked flip-flop coupled to the first multiplexor; and
a second multiplexor coupled to the clocked flip-flop.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein:
the first multiplexor of the second wrapper cell comprises a first input terminal coupled to the output terminal of the logic block, and a second input terminal coupled to an output terminal of the clocked flip-flop of the second wrapper cell;
the first multiplexor of the second wrapper cell is controlled by the first control signal;
the second multiplexor of the second wrapper cell comprises a first input terminal coupled to an output terminal of the first multiplexor of the second wrapper cell, and a second input terminal coupled to the output terminal of the clocked flip flop of the first wrapper cell;
the second input terminal of the second multiplexor of the second wrapper cell is configured to receive the scan path signal;
the second multiplexor of the second wrapper cell is controlled by the second control signal; and
an output terminal of the second multiplexor of the second wrapper cell is coupled to an input terminal of the clocked flip-flop of the second wrapper cell.

### Claim 16 (depends on 1)

The apparatus of claim 1, further comprising a first power domain including the logic block, the wrapper cell, the isolation cell, and the power control unit, wherein an output terminal of the isolation cell is coupled to an input terminal of a level shifter circuit of a second power domain.

### Claim 17

A multi-power domain multi-power isolation system, comprising:
a first power domain comprising a first logic block, a first plurality of wrapper cells coupled to the first logic block, a plurality of isolation cells, and a power control unit; and
a second power domain comprising a second logic block, a second plurality of wrapper cells coupled to the second logic block, and a plurality of level-shifter cells,
wherein:
each isolation cell from among the plurality of isolation cells is coupled to a corresponding wrapper cell from among the first plurality of wrapper cells;
each level-shifter cell from among the plurality of level-shifter cells is coupled to a corresponding wrapper cell from among the second plurality of wrapper cells;
an output terminal of each isolation cell from among the plurality of isolation cells is coupled to an input terminal of each level-shifter cell from among the plurality of level-shifter cells; and
the power control unit is coupled to the plurality of isolation cells in the first power domain.

### Claim 18 (depends on 17)

The multi-power domain multi-power isolation system of claim 17, wherein the power control unit is configured to receive a DFT internal core test mode control signal and a clamp control signal, and to control the plurality of isolation cells dependent on the DFT internal core test mode control signal and the clamp control signal.

### Claim 19 (depends on 18)

The multi-power domain multi-power isolation system of claim 18, wherein the power control unit is configured to place the plurality of isolation cells into an internal core test mode dependent on the DFT internal core test mode control signal.

### Claim 20 (depends on 19)

The multi-power domain multi-power isolation system of claim 19, wherein the internal core test mode includes a functional debug test mode that uses scan chain infrastructure for diagnosing a root cause of functional failure, and wherein the power control unit is configured to place the plurality of isolation cells into the functional debug test mode dependent on a functional debug test mode control signal.