# US 10,310,012 B2 · Lightweight, low overhead debug bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,310,012 B2 - Document ID: US10310012B2 - Status: Granted - Kind: B2 - Application number: 15/473,593 - Filed: 2017-03-29 - Published: 2018-06-21 - Granted: 2019-06-04 - Earliest claimed: 2016-12-21 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Lawrence H. Rubin; David C. Tannenbaum - Web page: https://patentgrep.com/patent/US10310012B2 ## CPC - G01R 31/31704: {Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00)} - G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)} - G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) - G06F 11/364: {tracing values on a bus} - G06F 11/3648: {using additional hardware} - G06F 11/3656: {using a specific debug interface} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus. ## Claims ### Claim 1 An apparatus comprising: an interconnect bus configured to connect to combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock; an interconnect-to-debug bus interface configured to translate communications between the interconnect bus and a debug bus; the debug bus comprising a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock; and wherein each of the plurality of debug wrapper circuits is configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein each of the debug wrapper circuits comprises: a designed-for-debug interface circuit configured to, upon activation by the debug bus, time multiplex a first number of non-invasive signals from a respective combinatorial logic block to a second number of debug output signals. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein each of the debug wrapper circuits comprises: a comparator configured to determine, based upon an fixed identifier, if a respective debug wrapper circuit is activated by the debug bus; and a multiplexer configured to, based upon whether or not the respective debug wrapper circuit is activated, forward a communication on the debug bus to a next debug wrapper circuit, or place the non-invasive input from the respective combinatorial logic block on the debug bus. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the debug bus is configured to transmit a debug wrapper circuit address on a first clock cycle, and transmit data on a second clock cycle. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the debug bus comprises a plurality of re-routing circuits, wherein each re-routing circuit is configured to bypass a respective debug wrapper circuit, such that the respective debug wrapper circuit is temporarily removed from the debug bus. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein each of the debug wrapper circuits comprises a synchronous circuit, operating at the core clock, and configured to separate the plurality of debug wrapper circuits from each other. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein each of the debug wrapper circuits is configured to only be activated if the interconnect bus is placed in a first transfer mode, wherein the first transfer mode is also employed for non-debug communication. ### Claim 8 A method comprising: transmitting a debug command via an interconnect bus configured to connect to combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock; translating the debug command between the interconnect bus and a debug bus, wherein the debug bus comprises a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication and that operate synchronous to the core clock; in response to the debug command, placing data from a selected debug wrapper circuit on the debug bus; and returning the data via the interconnect bus. ### Claim 9 (depends on 8) The method of claim 8, wherein each of the plurality of debug wrapper circuits is configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus. ### Claim 10 (depends on 9) The method of claim 9, wherein each of the debug wrapper circuits comprises: a designed-for-debug interface circuit configured to, upon activation by the debug bus, time multiplex a first number of non-invasive signals from a respective combinatorial logic block to a second number of debug output signals. ### Claim 11 (depends on 8) The method of claim 8, wherein each of the debug wrapper circuits comprises: a comparator configured to determine, based upon an fixed identifier, if a respective debug wrapper circuit is activated by the debug bus; and a multiplexer configured to, based upon whether or not the respective debug wrapper circuit is activated, forward a communication on the debug bus to a next debug wrapper circuit, or place the non-invasive input from the respective combinatorial logic block on the debug bus. ### Claim 12 (depends on 8) The method of claim 8, wherein placing data from a selected debug wrapper circuit on the debug bus comprises: transmitting a debug wrapper circuit address on a first clock cycle, and transmitting data on a second clock cycle. ### Claim 13 (depends on 8) The method of claim 8, wherein the debug bus comprises a plurality of re-routing circuits, wherein each re-routing circuit is configured to bypass a respective debug wrapper circuit, such that the respective debug wrapper circuit is temporarily removed from the debug bus. ### Claim 14 (depends on 8) The method of claim 8, translating the debug command between the interconnect bus and a debug bus comprises: activating the debug bus only if the interconnect bus is placed in a first transfer mode, and wherein the first transfer mode is also employed for non-debug communication. ### Claim 15 A system comprising: a graphic processing circuit configured to operate synchronous to a core clock, and manipulate and alter data in a memory to create images for output to a display device; an interconnect bus configured to connect to combinatorial logical blocks during normal operation of the graphic processing circuit and operate synchronous to the core clock; an interconnect-to-debug bus interface configured to translate communications between the interconnect bus and a debug bus; the debug bus comprising a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock; and wherein each of the plurality of debug wrapper circuits is configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus. ### Claim 16 (depends on 15) The system of claim 15, wherein each of the debug wrapper circuits comprises: a designed-for-debug interface circuit configured to, upon activation by the debug bus, time multiplex a first number of non-invasive signals from a respective combinatorial logic block to a second number of debug output signals. ### Claim 17 (depends on 15) The system of claim 15, wherein each of the debug wrapper circuits comprises: a comparator configured to determine, based upon a fixed identifier, if a respective debug wrapper circuit is activated by the debug bus; and a multiplexer configured to, based upon whether or not the respective debug wrapper circuit is activated, forward a communication on the debug bus to a next debug wrapper circuit, or place the non-invasive input from the respective combinatorial logic block on the debug bus. ### Claim 18 (depends on 15) The system of claim 15, wherein the debug bus is configured to transmit a debug wrapper circuit address on a first clock cycle, and transmit data on a second clock cycle. ### Claim 19 (depends on 15) The system of claim 15, wherein the debug bus comprises a plurality of re-routing circuits, wherein each re-routing circuit is configured to bypass a respective debug wrapper circuit, such that the respective debug wrapper circuit is temporarily removed from the debug bus. ### Claim 20 (depends on 15) The system of claim 15, wherein each of the debug wrapper circuits is configured to only be activated if the interconnect bus is placed in a first transfer mode, wherein the first transfer mode is also employed for non-debug communication.