# US 10,309,925 B2 · FET biosensor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,309,925 B2 - Document ID: US10309925B2 - Status: Granted - Kind: B2 - Application number: 15/143,262 - Filed: 2016-04-29 - Published: 2016-11-03 - Granted: 2019-06-04 - Earliest claimed: 2015-04-30 - Assignees: Imec Vzw - Applicants: Imec Vzw - Inventors: Nadine Collaert; Voon Yew Thean - Web page: https://patentgrep.com/patent/US10309925B2 ## CPC - G01N 27/4145: {specially adapted for biomolecules, e.g. gate electrode with immobilised receptors} - G01N 27/414: Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS - H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers} - H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices such as field-effect transistor devices configured for biomolecule sensing. In one aspect, a semiconductor chip comprises at least one field-effect transistor device which comprises a source, a drain, a gate stack and a channel region formed between the source and the drain. The gate stack only partially overlaps the channel region at the source side and/or at the drain side, such that a non-overlapped channel region at the source side and/or at the drain side is formed, where the non-overlapped channel region is configured for sensing biomolecules. ## Claims ### Claim 1 A method of fabricating a semiconductor chip configured for bio-sensing, the method comprising: obtaining a substrate comprising at least one semiconductor layer; providing a gate stack on the substrate; providing a doped drain region in and/or on the substrate; and providing a doped source region in and/or on the substrate, wherein the doped drain region and/or the doped source region have an underlap region laterally between the gate stack and the source region and/or between the gate stack and the drain region, such that the underlap region is configured for sensing biomolecules attached thereto. ### Claim 2 (depends on 1) The method according to claim 1, wherein providing the doped source region and/or providing the doped drain region includes performing a tilted ion implantation. ### Claim 3 (depends on 1) The method according to claim 1, further comprising, prior to providing the doped source region and/or providing the doped drain region, providing a spacer adjacent the gate stack at a side oriented towards the source region and/or a spacer adjacent the gate stack at a side oriented towards the drain region. ### Claim 4 (depends on 3) The method according to claim 3, wherein providing the doped source region and/or providing the doped drain region comprises growing an in-situ doped semiconductor layer. ### Claim 5 (depends on 3) The method according to claim 3, wherein providing the doped source region and/or providing the doped drain region comprises depositing a doped spin-on glass and outdiffusing dopants from the doped spin-on glass into the source region and/or the drain region. ### Claim 6 (depends on 3) The method according to claim 3, further comprising, after providing the doped source region and/or providing the doped drain region, removing the spacer at the side of the gate stack oriented towards the source region and/or removing the spacer at the side of the gate stack oriented towards the drain region. ### Claim 7 (depends on 1) The method according to claim 1, further comprising back end-of-the-line (BEOL) processing of the semiconductor chip. ### Claim 8 (depends on 1) The method according to claim 1, wherein providing the doped drain region includes covering a source side of the substrate such that the source side is not doped or further doped with a source dopant. ### Claim 9 A semiconductor chip configured for bio-sensing, the semiconductor chip comprising: at least one field-effect transistor (FET) device comprising a source, a drain, a gate stack and a channel region formed between the source and the drain, wherein the gate stack partially overlaps the channel region at a source side and/or at a drain side, such that a non-overlapped channel region is formed at the source side and/or at the drain side that is configured for sensing biomolecules. ### Claim 10 (depends on 9) The semiconductor chip according to claim 9, further comprising a spacer formed on the substrate between the gate stack and the drain. ### Claim 11 (depends on 9) The semiconductor chip according to claim 9, wherein the gate stack overlaps the drain. ### Claim 12 (depends on 9) The semiconductor chip according to claim 9, further comprising a reference FET having a gate stack which completely overlaps the channel. ### Claim 13 (depends on 9) The semiconductor chip according to claim 9, wherein the at least one FET comprises a backgate. ### Claim 14 (depends on 9) The semiconductor chip according to claim 9, wherein the channel region has an increased body factor. ### Claim 15 (depends on 9) The semiconductor chip according to claim 9, wherein the non-overlapped channel region comprises a semiconductor surface having formed thereon molecules having functional groups configured to bind to the biomolecules. ### Claim 16 (depends on 9) The semiconductor chip according to claim 9, wherein the channel region is undoped. ### Claim 17 (depends on 9) A method of using the semiconductor chip according to claim 9 for biomolecule sensing. ### Claim 18 (depends on 17) The method of claim 17, wherein the semiconductor chip comprises a backgate, and wherein a sub-threshold sweep is adjusted by adjusting a voltage on the backgate.