Logarithm and power (exponentiation) computations using modern computer architectures

A computer-implemented method for using hardware instructions to accelerate evaluation of mathematical functions, the method comprising:

• executing, on a first processing resource, a set of hardware instructions to receive an input comprising a specified degree for a polynomial and an input vector including multiple scalar input values, wherein each scalar input value is represented by a double-precision binary floating-point representation;
• and
• executing, on a second processing resource configured to support a single instruction multiple data (SIMD) processing, a first SIMD instruction to extract a mantissa and an exponent from the floating point representation of the real number for each input value in the input vector during the same Central Processing Unit (CPU) cycle;
• executing, on a third processing resource configured to support the SIMD processing, a second SIMD instruction to approximate a function of a logarithm of a mantissa of the real number for each input value in the input vector during the same CPU cycle, wherein approximation is performed by utilizing a polynomial having the specified degree, and wherein the polynomial is based on the mantissa;
• executing, on a fourth processing resource configured to support the SIMD processing, third SIMD instruction to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a first value for each input value in the input vector during the same CPU cycle;
• executing, on the fourth processing resource configured to support the SIMD processing, a fourth SIMD instruction to subtract an exponent bias from the first value, wherein the exponent bias is based on the floating point representation of the real number for each input value in the input vector during the same CPU cycle;
• and
• executing, on the fourth processing resource configured to support the SIMD processing, a fifth SIMD instruction to multiply the first value by a precomputed constant to calculate a second value comprising an approximate logarithm of the real number for each input value in the input vector during the same CPU cycle.

A computer program product for accelerating evaluation of mathematical function, the computer program product comprising:

• a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions readable by a processor system to cause the processor system to perform a method comprising:
• executing, on a first processing resource, a set of hardware instructions to receive an input comprising a specified degree for a polynomial and an input vector including multiple scalar input values, wherein each scalar input value is represented by a double-precision binary floating-point representation;
• and
• executing, on a second processing resource configured to support a single instruction multiple data (SIMD) processing, a first SIMD instruction to extract a mantissa and an exponent from the floating point representation of the real number for each input value in the input vector during the same Central Processing Unit (CPU) cycle;
• executing, on a third processing resource configured to support the SIMD processing, a second SIMD instruction to approximate a function of a logarithm of a mantissa of the real number for each input value in the input vector during the same CPU cycle, wherein approximation is performed by utilizing a polynomial having the specified degree, and wherein the polynomial is based on the mantissa;
• executing, on a fourth processing resource configured to support the SIMD processing, third SIMD instruction to combine the approximate function of the logarithm of the mantissa of the real number and the exponent for calculating a first value for each input value in the input vector during the same CPU cycle;
• executing, on the fourth processing resource configured to support the SIMD processing, a fourth SIMD instruction to subtract an exponent bias from the first value for each input value in the input vector during the same CPU cycle, wherein the exponent bias is based on the floating point representation of the real number;
• and
• executing, on the fourth processing resource configured to support the SIMD processing, a fifth SIMD instruction to multiply the first value by a precomputed constant to calculate a second value comprising an approximate logarithm of the real number for each input value in the input vector during the same CPU cycle.