Digital filter with a pipeline structure operating in multiple clock domains, and a corresponding device
AssigneeSTMicroelectronics S.r.l.
InventorFrancesco Pirozzi
Life of this patent
Estimating the term…
Abstract
A digital filter with a pipeline structure includes processing structures timed by respective clock signals. Each processing structure in turn is formed by a number of processing modules for processing input samples. A phase generator aligns the processing modules with the input samples so that each input sample is processed by a respective one of the processing modules. An up-sampling buffer and a down-sampling buffer are used when the processing structures operate at different clock frequencies (thus implementing different clock domains) so as to convert signal samples between the clock domains for processing in the processing structures.
Claims18
A digital filter, comprising:
- a first filter module operating with a first clock signal on first signal samples;
- a second filter module operating with a second clock signal on second signal samples, wherein a frequency of the second clock signal is different from a frequency of the first clock signal;
- a first re-sampling module having an input coupled to an output of the first filter module and an output coupled to an input of the second filter module, said first re-sampling module comprising:
- up-sampling and down-sampling buffers activatable in response to said first and second filter modules operating at different clock frequencies,
- wherein said up-sampling and down-sampling buffers are configured to convert signal samples between the frequency of the first clock signal and the frequency of the second clock signal.
A digital filter, comprising:
- a first memory including a first plurality of memory modules rotatable in response to a first clock at a first frequency and configured to receive first signal samples and output second signal samples;
- a down-sampling buffer having an input coupled to an output of the first memory and configured to down-sample the second signal samples to generate third signal samples;
- a second memory including a second plurality of memory modules rotatable in response to a second clock at a second frequency and configured to receive fourth signal samples derived from said third signal samples and output fifth signal samples;
- an up-sampling buffer having an input coupled to an output of the second memory and configured to up-sample the fifth signal samples to generate sixth signal samples;
- and
- a summation module configured to sum said sixth signal samples with input signal samples to generate said first signal samples.
A digital filter, comprising:
- a first memory including a first plurality of memory modules rotatable in response to a first clock at a first frequency and configured to receive first signal samples and output second signal samples;
- a down-sampling buffer having an input coupled to an output of the first memory and configured to generate third signal samples from said second signal samples;
- a second memory including a second plurality of memory modules rotatable in response to a second clock at a second frequency and configured to receive the third signal samples and output fourth signal samples;
- and
- an up-sampling buffer having an input coupled to an output of the second memory and configured to generate fifth signal samples;
- wherein the first signal samples are derived from input signal samples and the fifth signal samples.
Dependencies are inferred from the claim text.