Clock switch device and system-on-chip having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHye-Won Shim, Dong-Uk Park, Phil-Jae Jeon, Sang-Woo Pae, Da Ahn
Life of this patent
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Abstract
A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.
Claims20
A clock switch device, comprising:
- a control circuit to receive a clock signal having an unstable frequency and a stable frequency, to deactivate an output enable signal when a frequency of the clock signal varies and has the unstable frequency and to activate the output enable signal when the frequency of the clock signal is maintained without change and has the stable frequency;
- and
- a tri-state buffer to receive the clock signal, to maintain an output electrode at a high impedance state when the output enable signal is deactivated and to buffer the clock signal and output the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated, wherein
- the unstable frequency of the clock signal has at least a higher frequency than the stable frequency of the clock signal.
A system-on-chip, comprising:
- a clock signal generator to generate a clock signal having an unstable frequency and a stable frequency;
- a clock switch device to receive the clock signal, to stop outputting the clock signal when a frequency of the clock signal varies and has the unstable frequency and to buffer the clock signal and output the buffered clock signal as an output clock signal when the frequency of the clock signal is maintained without change and has the stable frequency;
- and
- a functional block to receive the output clock signal and to operate in synchronization with the output clock signal, wherein
- the unstable frequency of the clock signal has a least a higher frequency than the stable frequency of the clock signal.
A clock switch device, comprising:
- a control circuit to output a first control signal when a frequency of a clock signal is in a first state and has an unstable frequency and to output a second control signal when the frequency of the clock signal is in a second state and has a stable frequency, wherein the first state corresponds to when the clock signal varies and has the unstable frequency and the second state corresponds to when the clock signal is maintained and has the stable frequency;
- and
- a buffer to receive the clock signal, to stop outputting the clock signal in response to the first control signal and to buffer the clock signal and output the buffered clock signal as an output clock signal in response to the second control signal, wherein
- the unstable frequency of the clock signal has at least a higher frequency than the stable frequency of the clock signal.
Dependencies are inferred from the claim text.