Bandwidth-monitored frequency hopping within a selected DRAM operating point
AssigneeQUALCOMM Incorporated
InventorsRichard Stewart, Dexter Chun
Life of this patent
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Abstract
Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.
Claims30
A method for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin, the method comprising:
- receiving a selected voltage/frequency bin of a plurality of predefined voltage/frequency bins for operating a memory bus electrically coupling a memory controller to a dynamic random access memory, each voltage/frequency bin including a plurality of predefined frequencies;
- monitoring a bandwidth of the memory bus while operating at the selected voltage/frequency bin;
- and
- based on the monitored bandwidth, frequency switching a clock for the memory bus between a plurality of the predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth by maintaining an average clock frequency.
A system for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin, the method comprising:
- means for receiving a selected voltage/frequency bin of a plurality of predefined voltage/frequency bins for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM), each voltage/frequency bin including a plurality of predefined frequencies;
- means for monitoring a bandwidth of the memory bus while operating at the selected voltage/frequency bin;
- and
- means for frequency switching a clock for the memory bus between a plurality of the predefined frequencies within the selected voltage/frequency bin based on the monitored bandwidth to maintain a target bandwidth by maintaining an average clock frequency.
A computer program embodied in a non-transitory computer readable medium and executed by a processor for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin, the computer program comprising logic configured to:
- receive a selected voltage/frequency bin of a plurality of predefined voltage/frequency bins for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM), each voltage/frequency bin including a plurality of predefined frequencies;
- monitor a bandwidth of the memory bus while operating at the selected voltage/frequency bin;
- and
- frequency switch a clock for the memory bus between a plurality of the predefined frequencies within the selected voltage/frequency bin based on the monitored bandwidth to maintain a target bandwidth by maintaining an average clock frequency.
A system for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin, the system comprising:
- a dynamic clock and voltage scaling (DCVS) controller configured to select one of a plurality of voltage/frequency bins of a plurality of predefined voltage/frequency bins for operating a memory bus, each voltage/frequency bin including a plurality of predefined frequencies;
- a memory controller electrically coupled to a dynamic random access memory (DRAM) via the memory bus;
- and
- a dynamic frequency planning module in communication with the memory controller and the DCVS controller, the dynamic frequency planning module comprising logic configured to:
- receive the selected voltage/frequency bin from the DCVS controller;
- monitor a bandwidth of the memory bus while operating at the selected voltage/frequency bin;
- and
- frequency switch a clock for the memory bus between a plurality of the predefined frequencies within the selected voltage/frequency bin based on the monitored bandwidth to maintain a target bandwidth by maintaining an average clock frequency.
Dependencies are inferred from the claim text.