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US 10,296,067 B2Granted
Enhanced dynamic clock and voltage scaling (DCVS) scheme
AssigneeQUALCOMM Incorporated
InventorsHee Jun Park, Cristian Duroiu
Life of this patent
Estimating the term…
Abstract
In certain aspects, a method for frequency scaling comprises determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources. The method also comprises increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold. This may be done, for example, to increase the time duration of an idle mode for the one or more shared resources and achieve an overall power reduction for a system including the multiple processors, the one or more shared resources, and/or other function blocks.
Claims21
A method for frequency scaling, comprising:
- determining whether only a subset of multiple processors in a system on a chip (SoC) is active using a resource manager in the SoC, wherein the multiple processors share one or more resources and the subset is less than the number of multiple processors in the SoC, and each of the multiple processors is coupled to a respective dynamic clock and voltage scaling (DCVS) circuitry;
- and
- increasing a frequency of at least one processor in the subset of the multiple processors with the resource manager and respective DCVS circuitry coupled to the at least one processor if a determination is made by the resource manager that only the subset of the multiple processors is active and the remaining processors of the number of multiple processors outside the subset are idle, and the frequency of the at least one processor is below a frequency threshold;
- wherein the subset of the multiple processors includes one or more central processing units (CPUs), and one or more of the multiple processors outside the subset include at least one of a display processor, a video encoder/decoder, or a graphics processing unit (GPU), and the increasing of the frequency of the at least one processor in the subset is configured to increase an idle time of the shared one or more resources during at least one time frame by increasing the speed of the at least one processor in the subset to be able to enter an idle state at a time less than the total time duration of the least one time frame.
1 more element
An apparatus for frequency scaling, comprising:
- means for determining whether only a subset of multiple processors in a system on a chip (SoC) is active using a resource manager in the SoC, wherein the multiple processors share one or more resources and the subset is less than the number of multiple processors in the SoC, and each of the multiple processors is coupled to a respective dynamic clock and voltage scaling (DCVS) circuitry;
- and
- means for increasing a frequency of at least one processor in the subset of the multiple processors with the resource manager and respective DCVS circuitry coupled to the at least one processor if a determination is made by the resource manager that only the subset of the multiple processors is active and the remaining processors of the number of multiple processors outside the subset are idle, and the frequency of the at least one processor is below a frequency threshold;
- wherein the subset of the multiple processors includes one or more central processing units (CPUs), and one or more of the multiple processors outside the subset include at least one of a display processor, a video encoder/decoder, or a graphics processing unit (GPU), and the means for increasing of the frequency of the at least one processor in the subset is configured to increase an idle time of the shared one or more resources during at least one time frame by increasing the speed of the at least one processor in the subset to be able to enter an idle state at a time less than the total time duration of the least one time frame.
1 more element
A system on a chip (SoC), comprising:
- multiple processors in the SoC, wherein the multiple processors share one or more resources;
- and
- a resource manager configured to:
- determine whether only a subset of the multiple processors in the system is active wherein the subset is less than the number of multiple processors in the SoC, and each of the multiple processors is coupled to a respective dynamic clock and voltage scaling (DCVS) circuitry, and
- to increase a frequency of at least one processor in the subset of the multiple processors if a determination is made by the resource manager that only the subset of the multiple processors is active and the remaining processors of the number of multiple processors outside the subset are idle, and the frequency of the at least one processor is below a frequency threshold;
- wherein the subset of the multiple processors includes one or more central processing units (CPUs), and one or more of the multiple processors outside the subset include at least one of a display processor, a video encoder/decoder, or a graphics processing unit (GPU), and increasing the frequency of the at least one processor is operable for increasing an idle time during at least one time frame of one or more resources shared by the multiple processors by increasing the speed of the at least one processor in the subset to be able to enter an idle state at a time less than the total time duration of the least one time frame.
3 more elements
Dependencies are inferred from the claim text.