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US 10,295,597 B2Granted
Semiconductor device and scan test method including writing and reading test data
AssigneeRenesas Electronics Corporation
InventorsYoichi Maeda, Jun Matsushima, Hiroki Wada
Life of this patent
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Abstract
A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.
Claims15
A semiconductor device comprising:
- a FIFO (First In First Out);
- a test data write circuit connected to the FIFO, the test data write circuit sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal;
- and
- a test control circuit connected to the test data write circuit, the test control circuit in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal, which is not synchronous with the first clock signal, to perform a scan test of a circuit to be tested,
- wherein
- the circuit to be tested has a scan chain for performing the scan test, and performs a scan shift operation in synchronization with the second clock signal and thereby reads test data from the FIFO and scans the test data into the scan chain, and scans out test result data stored in the scan chain,
- the test data write circuit sequentially writes the plurality of test data and a plurality of mask data respectively corresponding to the plurality of data to the FIFO in synchronization with the first clock signal,
- the semiconductor device further includes a test result processing circuit to which the test result data scanned out of the scan chain is input, and
- the test result processing circuit includes a mask circuit that, when the test data is scanned into the scan chain, reads mask data corresponding to the test data from the FIFO, and masks, by the read mask data, the test result data to be scanned out when the test data is scanned into the scan chain, and thereby fixes the data to Low or High.
6 more elements
A semiconductor device comprising,
- a FIFO (First In First Out);
- a test data write circuit connected to the FIFO the test data write circuit sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal;
- and
- a test control circuit connected to the test data write circuit, the test control circuit in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal, which is not synchronous with the first clock signal, to perform a scan test of a circuit to be tested,
- wherein
- the semiconductor device includes a plurality of circuits to be tested,
- each of the plurality of circuits to be tested has a scan chain for performing the scan test, and performs a scan shift operation in synchronization with the second clock signal and thereby scans the test data read by the test control circuit into the scan chain, and
- the semiconductor device further includes an input selection circuit that selects a circuit to be tested specified by the test control circuit from the plurality of circuits to be tested as a circuit to which the test data read from the FIFO is to be input.
5 more elements
A semiconductor device comprising:
- a FIFO (First In First Out);
- a test data write circuit connected to the FIFO, the test data write circuit sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal;
- and
- a test control circuit connected to the test data write circuit, the test control circuit in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal, which is not synchronous with the first clock signal, to perform a scan test of a circuit to be tested,
- wherein
- the circuit to be tested is a first circuit to be tested,
- the test control circuit is a first test control circuit, and
- the semiconductor device further includes
- a second test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a third clock signal, which is not synchronous with the first clock signal and the second clock signal, and performs a scan test of a second circuit to be tested, and
- a selection circuit that selects any one of the first test control circuit and the second test control circuit as a test control circuit to perform the scan test.
7 more elements
Dependencies are inferred from the claim text.