Method and system for generating validation tests
AssigneeCadence Design Systems, Inc.
InventorMeir Ovadia
Life of this patent
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Abstract
A method for generating a validation test may include using a processor, identifying, in a scenario for validation testing, a plurality of actions that address a single resource in a conflicting manner; and automatically generating target code of the scenario that includes one or a plurality of resource management commands so as to prevent conflicting addressing of that resource by said plurality of actions.
Claims9
A method for generating a validation test, the method comprising:
- using a processor, identifying, in a combined scenario of a plurality of scenarios having different run times to be executed in parallel and in repeated loops, each scenario of the plurality of scenarios having been validated in simulation or emulation testing, the combined scenario for inclusion in a post silicon validation test of a system on chip (SOC), each scenario comprising one or more actions that are to be performed on the SOC, a plurality of the actions of different scenarios of the plurality of scenarios in one of the loops that concurrently address a single resource of the SOC, the single resource being limited to sequential addressing and comprising a memory address or a device of the SOC;
- and
- automatically by the processor generating target code of the validation test that includes one or a plurality of resource management commands, each of the resource management commands configured to prevent the concurrent addressing of the single resource by said plurality of the actions.
A non-transitory computer readable storage medium for generating a validation test, having stored thereon instructions that when executed by a processor will cause the processor to:
- identify, in a combined scenario of a plurality of scenarios having different run times to be executed in parallel and in repeated loops, each scenario of the plurality of scenarios having been validated in simulation or emulation testing, the combined scenario for inclusion in a post silicon validation test of a system on chip (SOC), each scenario comprising one or more actions that are are to be performed on the SOC, a plurality of the actions of different scenarios of the plurality of scenarios in one of the loops that concurrently address a single resource of the SOC, the single resource being limited to sequential addressing and comprising a memory address or a device of the SOC;
- and
- automatically generate target code of the validation test that includes one or a plurality of resource management commands, each of the resource management commands configured to prevent the concurrent addressing of the single resource by said plurality of the actions.
A system for generating a validation test, the system comprising:
- a memory and
- a processor configured to:
- using a processor, identify, in a combined scenario of a plurality of scenarios having different run times to be executed in parallel and in repeated loops, each scenario of the plurality of scenarios having been validated in simulation or emulation testing, the combined scenario for inclusion in a post silicon validation test of a system on chip (SOC), each scenario comprising one or more actions that are are to be performed on the SOC, a plurality of the actions of different scenarios of the plurality of scenarios in one of the loops that concurrently address a single resource of the SOC, the single resource being limited to sequential addressing and comprising a memory address or a device of the SOC;
- and
- automatically generate target code of the validation test that includes one or a plurality of resource management commands, each of the resource management commands configured to prevent the concurrent addressing of the single resource by said plurality of the actions.
Dependencies are inferred from the claim text.