System and method for testing and configuration of an FPGA

A Field Programmable Gate Array capable of implementing a logic function said Field Programmable Gate Array comprising a plurality of hardware lookup tables, the select lines or outputs of each lookup table being programmably interconnected with the select lines or outputs of another said lookup table by means of a plurality of programmable switches said Field Programmable Gate Array further comprising:

• a plurality of flip flops in a shift register configuration, each said Lookup table having at least one input coupled to an output of a respective said flip flop, and each said programmable switch coupled to an output of a further respective said flip flop;
• and
• wherein said Field Programmable Gate Array is arranged to operate in a first mode in which said shift register is loaded with predefined test values, and a second mode in which said shift register is loaded with values implementing said logic function.