Integrated circuit verification using parameterized configuration
AssigneeUniversiteit Gent
InventorsAlexandra Kourfali, Dirk Stroobandt
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Abstract
A method for debugging and a method for testing a circuit design on a programmable logic device is disclosed, making use of a parameterized configuration. A corresponding system also is disclosed.
Claims20
A method for debugging a circuit design on a programmable logic device, the method being executed by a processor executing computer readable code stored on a non-transitory computer-readable medium or the method being implemented on a hardware system comprising a circuit design component and a debug component, the method comprising:
- inserting multiplexers in an existing design at signal locations whose value should be observable in a debugging phase, where selection bits of the multiplexers are parameters defining when a signal is observable and when a signal is not observable,
- compiling an enhanced version of a design specification of an integrated circuit to a specification of a parameterized version of a configuration for the programmable logic device, with the multiplexer selection bits as parameters,
- programming the programmable logic device in accordance with said specification of the parameterized version of the configuration, said programming comprising adding a plurality of tunable connections to the specification of the parameterized version of the configuration for routing a plurality of internal signals to at least one trace buffer, each tunable connection allowing routing exactly one internal signal of said plurality of internal signals to exactly one trace buffer of said at least one trace buffer when the tunable connection is set to an active state by a corresponding parameter, and
- debugging the programmable logic device while executing said specification of the parameterized version of the configuration, wherein said debugging comprises reconfiguring the programmable logic device for selecting a subset of the plurality of internal signals to route to the at least one trace buffer, wherein this reconfiguring comprises applying a parameterized version of a run-time reconfiguration of at least one routing configuration cell of the programmable logic device in accordance with said specification of the parameterized version of the configuration.
A method for debugging a circuit design on a programmable logic device, the method being executed by a processor executing computer readable code stored on a non-transitory computer-readable medium or the method being implemented on a hardware system comprising a circuit design component and a debug component, the method comprising:
- inserting multiplexers in an existing design specification at signal locations whose value should be selectively observable during debugging, where selection bits of the multiplexers are parameters defining when a signal is observable and when a signal is not observable, thereby forming an enhanced version of a design specification of an integrated circuit,
- compiling the enhanced version of the design specification of the integrated circuit to a specification of a parameterized version of a configuration for a programmable logic device, with the multiplexer selection bits as parameters,
- programming the programmable logic device in accordance with said specification of the parameterized version of the configuration, and
- debugging the programmable logic device while executing said specification of the parameterized version of the configuration, wherein said debugging comprises applying a parameterized version of a run-time configuration of the programmable logic device in accordance with said specification of the parameterized version of the configuration taking into account the selection bits of the multiplexers in accordance with signals to be observed during the debugging.
A method for generating a test set of a circuit design on a programmable logic device, the method being executed by a processor executing computer readable code stored on a non-transitory computer-readable medium or the method being implemented on a hardware system comprising a circuit design component and a debug component, the method comprising
- inserting multiplexers in an existing design at signal locations where a signal fault can be generated,
- where selection bits of the multiplexers are parameters defining when a signal fault occurs and when no signal fault occurs, thus forming an enhanced version of a design specification of an integrated circuit.
A debugging system for debugging a circuit design on a programmable logic device, the debugging system comprising:
- a circuit design component adapted for implementing a parameterized specification of a programmable logic device for a circuit design to be debugged, the parameterized specification comprising a plurality of tunable connections for routing a plurality of internal signals to at least one trace buffer, each tunable connection being adapted for routing exactly one internal signal of said plurality of internal signals to exactly one trace buffer of said at least one trace buffer when the tunable connection is set to an active state by a corresponding parameter, and
- a debugging component configured for debugging the programmable logic device while executing said specification of the parameterized version of the configuration, wherein said debugging component is adapted for reconfiguring the programmable logic device for selecting a subset of the plurality of internal signals to route to the at least one trace buffer, wherein this reconfiguring comprises applying a parameterized run-time reconfiguration of at least one routing configuration cell of the programmable logic device in accordance with said specification of the parameterized version of the configuration.
A test set generation system for generating a test set of a circuit design on a programmable logic device, the test set generation system comprising
- a circuit design component adapted for inserting multiplexers in an existing design at signal locations where a signal fault can be generated,
- where selection bits of the multiplexers are parameters defining when a signal fault occurs and when a signal fault does not occur.
Dependencies are inferred from the claim text.