Wafer testing without direct probing

A semiconductor wafer, comprising:

• (A) a region comprising a plurality of integrated circuit die locations organized in rows and columns;
• (B) first scribe lines separating the rows of integrated circuit die locations;
• (C) second scribe lines separating the columns of integrated circuit die locations;
• (D) a test integrated circuit die occupying at least one of the integrated circuit die locations, the test integrated circuit die comprising:
• (i) a plurality of probe pads,
• (ii) a master test circuit coupled to the probe pads, and
• (iii) a first routing circuit coupled to the master test circuit, wherein the first routing circuit is configured to be coupled to a routing circuit in at least one adjacent integrated circuit die location;
• (E) a plurality of product integrated circuit dies each occupying one of the integrated circuit die locations, each product integrated circuit die comprising:
• (i) a second routing circuit that is configured to be coupled to at least one routing circuit in an adjacent integrated circuit die location,
• (ii) a slave test circuit coupled to the second routing circuit, and
• (iii) a main circuit coupled to the slave test circuit;
• (F) one or more first conductors configured to electrically couple signals across at least one scribe line between the first routing circuit and the second routing circuit;
• and
• (G) a plurality of second conductors configured to electrically couple at least two power voltage levels across at least one scribe line.