On-chip measurement for phase-locked loop
AssigneeAnalog Devices Global
InventorsVamshi Krishna Chillara, Pablo Cruz Dato, Declan M. Dalton
Life of this patent
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Abstract
A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.
Claims18
A phase-locked loop operable in a plurality of modes, the phase-locked loop comprising:
- an oscillator configured to generate an oscillating output signal;
- and
- a loop filter configured to filter an output of a phase detector of the phase-locked loop;
- wherein an input to the oscillator is coupled to an output of the loop filter in a first mode;
- wherein the input to the oscillator is decoupled, at least in part, from the output of the loop filter in a second mode;
- and
- wherein the phase-locked loop is configured to output an indication of a frequency of the oscillating output signal based at least partly on the output of the loop filter in the second mode.
A method of testing a phase-locked loop, the method comprising:
- configuring an input of an oscillator of the phase-locked loop to be independent of an output of the oscillator in a test mode;
- providing a feedback path from an output of a phase detector to an input of the phase detector in the test mode;
- and
- providing an output from the feedback path to a test controller implemented on the same chip as the phase-locked loop.
Dependencies are inferred from the claim text.