Hybrid tracking of transaction read and write sets
AssigneeInternational Business Machines Corporation
InventorsMichael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum
Life of this patent
Estimating the term…
Abstract
Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a remote processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.
Claims18
A computer system comprising:
- a processing unit operatively coupled to memory;
- a tool in communication with the processing unit to track a processor instruction, the tool to:
- maintain a non-speculative indication of a non-speculative instruction stored in cache for a transaction by a first requestor;
- maintain a queue of at least one address corresponding to a speculatively executed instruction corresponding to a speculative member of a set selected from the group consisting of:
- a read set and a write set;
- perform a transaction interference resolution responsive to receipt of a request for data by a remote processor, including determine a potential transaction interference exclusively conflicting with the speculatively executed instruction;
- and
- hold a response to the received request until the speculatively executed instruction is in a state selected from the group consisting of:
- committed and flushed.
A computer program product for tracking a processor instruction, the computer program product comprising a computer readable storage device having program code embodied therewith, the program code executable by a processing unit to:
- maintain a non-speculative indication of a non-speculative instruction stored in cache for a transaction by a first requestor;
- maintain a queue of at least one address corresponding to a speculatively executed instruction corresponding to a speculative member of a set selected from the group consisting of:
- a read set and a write set;
- perform a transaction interference resolution responsive to receipt of a request for data by a remote processor, including determine a potential transaction interference exclusively conflicting with the speculatively executed instruction;
- and
- hold a response to the received request until the speculatively executed instruction is in a state selected from the group consisting of:
- committed and flushed.
A method for tracking a processor instruction comprising:
- maintaining a non-speculative indication of a non-speculative instruction stored in cache for a transaction by a first requestor;
- maintaining a queue of at least one address corresponding to a speculatively executed instruction corresponding to a speculative member of a set selected from the group consisting of:
- a read set and a write set;
- performing a transaction interference resolution responsive to receiving a request for data by a remote processor, including determining a potential transaction interference exclusively conflicting with the speculatively executed instruction;
- and
- holding a response to the received request until the speculatively executed instruction is in a state selected from the group consisting of:
- committed and flushed.
Dependencies are inferred from the claim text.