Reception interface circuits supporting multiple communication standards and memory systems including the same

A memory system comprising:

• a memory device;
• and
• a memory controller configured to control the memory device;
• wherein the memory device includes
• a termination circuit configured to change a termination mode in response to a termination control signal,
• a buffer configured to change a reception characteristic in response to a buffer control signal, and
• an interface controller configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode;
• wherein the termination circuit includes
• a first sub termination circuit configured to control an electrical connection between an input-output node and a first power supply voltage in response to a first switch control signal, and
• a second sub termination circuit configured to control an electrical connection between the input-output node and a second power supply voltage in response to a second switch control signal, the second power supply voltage lower than the first power supply voltage;
• and
• wherein the buffer includes
• a first reception buffer including a plurality of first differential input pairs of transistors, the plurality of first differential input pairs of transistors including both a first N-type differential input pair of NMOS transistors and a first P-type differential input pair of PMOS transistors,
• a second reception buffer including a single second differential input pair of transistors, the single second differential input pair of transistors being a P-type differential input pair of PMOS transistors, and
• a third reception buffer including a single third differential input pair of transistors, the single third differential input pair of transistors being an N-type differential input pair of NMOS transistors.

A memory device comprising:

• a reception interface circuit including a plurality of reception buffers and a termination circuit, the reception interface circuit configured to
• operate in a plurality of termination modes based on mode information stored at an internal circuit of the memory device, and
• set a reception characteristic for the reception interface circuit by selecting a reception buffer from among the plurality of reception buffers based on a selected one of the plurality of termination modes, each of the plurality of reception buffers having different reception characteristics;
• wherein the termination circuit includes
• a first sub termination circuit configured to control an electrical connection between an input-output node and a first power supply voltage in response to a first switch control signal, and
• a second sub termination circuit configured to control an electrical connection between the input-output node and a second power supply voltage in response to a second switch control signal, the second power supply voltage lower than the first power supply voltage;
• and
• wherein the plurality of reception buffers include
• a first reception buffer including a plurality of first differential input pairs of transistors, the plurality of first differential input pairs of transistors including both a first N-type differential input pair of NMOS transistors and a first P-type differential input pair of PMOS transistors,
• a second reception buffer including a single second differential input pair of transistors, the single second differential input pair of transistors being a P-type differential input pair of PMOS transistors, and
• a third reception buffer including a single third differential input pair of transistors, the single third differential input pair of transistors being an N-type differential input pair of NMOS transistors.