Differential physical layer device with testing capability
AssigneeMixel
InventorAshraf K. Takla
Life of this patent
Estimating the term…
Abstract
A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.
Claims20
A circuit, comprising:
- control and interface logic coupled to clock, data, control and test signals;
- transmitter and receiver clock circuits coupled to the control and interface logic;
- a single data transmitter coupled to the control and interface logic;
- a plurality of data receivers coupled to control and interface logic and the single data transmitter, the data receivers having a loop-back mode coupled to the single data transmitter for sequentially performing self-test on each data receiver, wherein the receiver has first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode;
- and
- switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating a transmitter on another side of a link during the second mode.
A MIPI differential physical (D-PHY) system, comprising:
- control and interface logic coupled to clock, data, control and test signals;
- transmitter and receiver clock circuits coupled to the control and interface logic;
- a single data transmitter coupled to the control and interface logic;
- and
- a plurality of data receivers coupled to control and interface logic and the single data transmitter, the data receivers having a loop-back mode coupled to the single data transmitter for sequentially performing self-test on each data receiver.
A method for testing a MIPI differential physical (D-PHY) system having a control and interface logic coupled to clock, data, control and test signals;
- transmitter and receiver clock circuits coupled to the control and interface logic;
- a single data transmitter coupled to the control and interface logic;
- and a plurality of data receiver coupled to control and interface logic and the single data transmitter, the data receivers having a loop-back mode coupled to the single data transmitter for sequentially performing self-test on each data receiver, comprising:
- setting the receiver to the loop-back mode;
- driving the receiver with the test signal from a transmitter;
- and
- determining if the receiver output matches the transmitter output.
Dependencies are inferred from the claim text.