High gain load circuit for a differential pair using depletion mode transistors

A depletion mode differential pair gain stage comprising:

• a differential pair of depletion-mode transistors, including a first and a second depletion mode transistor, the first and second depletion mode transistors of the differential pair of depletion mode transistors having a gate, source, and a drain, the differential pair of depletion-mode transistors coupled at the source to form a common node;
• and
• an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of the first and second depletion mode transistors of the differential pair, wherein the active load includes a current source formed from a third depletion mode transistor coupled to an output node of the differential pair via a resistor, the current source electrically coupling the gate of the third depletion mode transistor to the drain of the second depletion mode transistor to source current from the third depletion mode transistor to the second depletion mode transistor via the resistor;
• wherein the active load includes a buffer formed from at least a fourth depletion mode transistor electrically coupling the drains of the first and second depletion mode transistors of the differential pair;
• wherein the buffer has a substantially unity gain, and the source of the fourth depletion mode transistor is connected to a drain of the first depletion mode transistor;
• and
• wherein the fourth depletion mode transistor has its gate electrically coupled to a source terminal of the third depletion mode transistor forming a source follower such that the gate of the fourth depletion mode transistor and the source terminal of the third depletion mode transistor are at the same potential.