Delay based comparator

A delay circuit, comprising:

• a first inverter coupled to a first transistor and a second transistor, the first inverter configured to receive a first intermediate delayed clock signal and generate a positive delayed clock signal to be received by a first negative-AND (NAND) gate of a comparator;
• a second inverter coupled to a third transistor and a fourth transistor, the second inverter configured to receive a second intermediate delayed clock signal and generate a negative delayed clock signal to be received by a second NAND gate of the comparator;
• and
• a pair of cross-coupled capacitors coupled to the first and second inverters;
• wherein:
• the first transistor is connected to the second transistor in parallel;
• the third transistor is connected to the fourth transistor in parallel;
• the resistance of the first transistor in parallel with the second transistor determines a delay in the positive delayed clock signal;
• and
• the resistance of the third transistor in parallel with the fourth transistor determines a delay in the negative delayed clock signal;
• wherein:
• the first transistor includes a first gate configured to receive a positive input signal;
• the second transistor includes a second gate configured to receive a negative reference signal;
• the third transistor includes a third gate configured to receive a negative input signal;
• and
• the fourth transistor includes a fourth gate configured to receive a positive reference signal.

A comparator, comprising:

• a differential input pair of transistors including a first input transistor and a second input transistor;
• and
• a delay circuit that includes:
• a first inverter coupled to a first transistor and a second transistor, the first inverter configured to receive a first intermediate delayed clock signal and generate a positive delayed clock signal to be received by the first input transistor;
• a second inverter coupled to a third transistor and a fourth transistor, the second inverter configured to receive a second intermediate delayed clock signal and generate a negative delayed clock signal to be received by the second input transistor;
• and
• a pair of cross-coupled capacitors coupled to the first and second inverters;
• wherein:
• the first inverter includes a first input terminal and a first output terminal;
• the second inverter includes a second input terminal and a second output terminal;
• the pair of cross-coupled capacitors includes a first capacitor and a second capacitor;
• the first input terminal is connected to a first terminal of the first capacitor;
• the second output terminal is connected to a second terminal of the first capacitor;
• the second input terminal is connected to a third terminal of the second capacitor;
• and
• the first output terminal is connected to a fourth terminal of the second capacitor;
• wherein:
• the first transistor includes a first drain;
• the second transistor includes a second drain;
• the third transistor includes a third drain;
• the fourth transistor includes a fourth drain;
• the first input terminal is connected to the first drain and the second drain;
• and
• the second input terminal is connected to the third drain and the fourth drain;
• wherein:
• the first transistor includes a first gate configured to receive a positive input signal;
• the second transistor includes a second gate configured to receive a negative reference signal;
• the third transistor includes a third gate configured to receive a negative input signal;
• the fourth transistor includes a fourth gate configured to receive a positive reference signal;
• the resistance of the first transistor is proportional to a voltage level of the positive input signal;
• the resistance of the second transistor is proportional to a voltage level of the negative reference signal;
• the resistance of the third transistor is proportional to a voltage level of the negative input signal;
• and
• the resistance of the fourth transistor is proportional to a voltage level of the positive reference signal.