Duty cycle correction scheme for complementary signals
AssigneeSanDisk Technologies LLC
InventorsPrimit Modi, Venkatesh Ramachandra, Tianyu Tang, Srinivas Rajendra
Life of this patent
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Abstract
A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.
Claims21
A circuit comprising:
- a complementary signal path circuit configured to receive a pair of complementary input signals and generate a pair of complementary output signals in response to receipt of the pair of complementary input signals, wherein the complementary signal path circuit comprises:
- an amplifier circuit configured to receive the pair of complementary input signals and generate at least one pair of complementary intermediate signals in response to receipt of the pair of complementary input signals;
- and
- a control circuit configured to:
- measure a duty cycle mismatch between the pair of complementary output signals;
- and
- based on the measured duty cycle mismatch, set at least one of:
- a gain of the amplifier circuit, or
- a high voltage level and a low voltage level to set a common mode voltage of the at least one pair of complementary intermediate signals.
A circuit comprising:
- an amplifier circuit configured to output an amplifier output signal in response to receipt of an input signal;
- a search circuit configured to search for a target current amount for a control current;
- and
- a current injection circuit configured to inject the control current at the target current amount into the amplifier circuit,
- wherein the amplifier circuit is configured to adjust a duty cycle of the amplifier output signal in response to receipt of the control current at the target current amount.
A system comprising:
- an amplifier circuit configured to generate at least one pair of clock signals;
- a data alignment circuit configured to generate an aligned data signal and a pair of output clock signals based on the at least one pair of clock signals;
- and
- a feedback circuit configured to:
- determine duty cycle distortion in the pair of output clock signals;
- and
- in response to the determination, control the amplifier circuit to adjust at least one characteristic of the at least one pair of clock signals to compensate for the duty cycle distortion.
A system comprising:
- an amplifier circuit comprising:
- a first branch configured to:
- receive a first input signal of a pair of input signals;
- and
- output a first intermediate signal of a pair of intermediate signals;
- and
- a second branch configured to:
- receive a second input signal of the pair of input signals;
- and
- output a second intermediate signal of the pair of intermediate signals;
- a data alignment circuit configured to generate a pair of output signals based on the pair of intermediate signals;
- and
- a control circuit configured to:
- measure a duty cycle mismatch between the pair of output signals;
- and
- based on the measured duty cycle mismatch, inject a control current into:
- the first branch to generate the first intermediate signal of the pair of intermediate signals with reduced gain and an increased common mode voltage;
- or
- the second branch to generate the second intermediate signal of the pair of intermediate signals with reduced gain and an increased common mode voltage.
Dependencies are inferred from the claim text.