Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof

A semiconductor structure, comprising:

• a first die comprising a three-dimensional memory device including a three-dimensional array of NAND memory elements;
• and
• a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate;
• wherein:
• the first die is bonded to the second die;
• gate structures of the CMOS devices of the second die are located between the three-dimensional array of NAND memory elements of the first die and the semiconductor substrate of the second die containing active regions separated by a channel of the CMOS devices;
• the first die further comprises an additional semiconductor substrate;
• an additional peripheral logic circuitry that includes additional CMOS devices is located on the additional semiconductor substrate, and is electrically coupled to at least one node of the three-dimensional memory device;
• and
• the additional CMOS devices are configured to operate at a higher voltage than the CMOS devices of the second die.

A semiconductor structure, comprising:

• a first die comprising a three-dimensional memory device including a three-dimensional array of NAND memory elements;
• and
• a second die comprising a semiconductor substrate, a peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate;
• wherein:
• the first die is bonded to the second die;
• and
• gate structures of the CMOS devices of the second die are located between the three-dimensional array of NAND memory elements of the first die and the semiconductor substrate of the second die containing active regions separated by a channel of the CMOS devices;
• first copper pads of the first die are bonded with second copper pads of the second die to provide multiple bonded pairs of a respective first copper pad and a respective second copper pad at an interface between the first die and the second die;
• the three-dimensional array of NAND memory elements is located within a two-dimensional array of vertical NAND strings;
• each vertical NAND string in the array of vertical NAND strings comprises charge storage elements controlled by word lines and a vertical semiconductor channel of which an end portion is connected to a respective bit line;
• a first subset of the first copper pads is electrically shorted to a respective bit line;
• and
• a second subset of the first copper pads is electrically shorted to a respective word line.

A method of forming a semiconductor structure, comprising:

• providing a first die comprising a three-dimensional memory device including a three-dimensional array of NAND memory elements;
• providing a second die comprising a semiconductor substrate and peripheral logic circuitry that includes complementary metal oxide semiconductor (CMOS) devices located on the semiconductor substrate;
• and
• forming a bonded assembly by bonding the first die to the second die;
• wherein:
• the first die further comprises a first dielectric material layer overlying, or underlying, the three-dimensional array of memory elements, and first copper pads embedded in the first dielectric material layer and electrically shorted to a respective node within the three-dimensional memory device;
• the second die further comprises a second dielectric material layer overlying, or underlying, the CMOS devices, and second copper pads embedded in the second dielectric material layer and electrically shorted to a respective node within the CMOS devices;
• and
• forming the bonded assembly comprises bonding the first copper pads with the second copper pads through copper interdiffusion to provide multiple bonded pairs of a respective first copper pad and a respective second copper pad at an interface between the first die and the second die.