Semiconductor memory device and method of operating the same
AssigneeSK hynix Inc.
InventorJin Yong Seong
Life of this patent
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Abstract
Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.
Claims18
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells;
- a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed;
- a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal and to receive an input signal from an external device through the ready/busy line;
- a peripheral circuit configured to perform the operation;
- and
- a control logic configured to control the peripheral circuit in response to the input signal,
- wherein the ready/busy line input mode control unit comprises:
- an input/output control unit configured to set the ready/busy line as one of an input line transferring the input signal and as an output line transferring the ready/busy signal;
- an input buffer configured to transfer the input signal inputted through the ready/busy line to the control logic;
- and
- a ready/busy pad configured to couple the ready/busy line to the external device.
A method of operating a semiconductor memory device including a plurality of registers, the method comprising:
- setting a ready/busy line of the semiconductor memory device as an input line;
- receiving, from an external device, a parameter set command for changing a value of at least one among the plurality of registers, an address of the at least one register, and data for the at least one register;
- determining whether the address of the at least one register is an address of a special register;
- and
- if the address of the at least one register is the address of the special register, executing the parameter set command in response to an input signal that is inputted through the ready/busy line set as the input line.
A semiconductor memory device, comprising:
- a ready/busy line configured as an input line to transfer an incoming signal from an external device to the semiconductor memory device, and as an output line to transfer a ready/busy signal from the semiconductor memory device to the external device;
- a ready/busy line input mode control unit configured to set the ready/busy line as one of the input line and the output line;
- a peripheral circuit configured to perform the operation;
- and
- a control logic configured to control the peripheral circuit in response to the input signal,
- wherein the ready/busy line input mode control unit comprises:
- an input/output control unit configured to set the ready/busy line as one of an input line transferring the input signal and as an output line transferring the ready/busy signal;
- an input buffer configured to transfer the input signal inputted through the ready/busy line to the control logic;
- and
- a ready/busy pad configured to couple the ready/busy line to the external device.
Dependencies are inferred from the claim text.