Energy efficient processor core architecture for image processor
AssigneeGoogle Inc.
InventorsAlbert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
Life of this patent
Estimating the term…
Abstract
An apparatus that includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Claims20
A computing device comprising:
- a stencil processor comprising a plurality of execution lanes;
- and
- a scalar lane that is configured to receive an instruction having multiple instruction opcodes, wherein the instruction comprises:
- (1) a scalar opcode corresponding to a scalar operation to be performed by the scalar lane, and (2) an execution lane opcode corresponding to one or more execution lane operations to be performed by each of the plurality of execution lanes,
- wherein, upon receiving the instruction, the scalar lane is configured to execute the scalar operation and broadcast the execution lane opcode to each of the plurality of execution lanes.
A method comprising:
- a stencil processor comprising a plurality of execution lanes;
- and
- receiving, by a scalar lane of a stencil processor having a scalar lane and a plurality of execution lanes, an instruction having multiple instruction opcodes, wherein the instruction comprises:
- (1) a scalar opcode corresponding to a scalar operation to be performed by the scalar lane, and (2) an execution lane opcode corresponding to one or more execution lane operations to be performed by each of the plurality of execution lanes;
- executing, by the scalar lane, the scalar operation corresponding to the scalar opcode;
- and
- broadcasting, by the scalar lane to each of the plurality of execution lanes, the execution lane opcode corresponding to the one or more execution lane operations.
Dependencies are inferred from the claim text.