Semiconductor device, memory circuit, method of manufacturing semiconductor device

A memory circuit, comprising:

• one of a non-volatile element or a volatile element,
• a switch element configured to control a flow of current via one of the non volatile element or the volatile element,
• wherein the switch element comprises:
• a first diffusion section in a semiconductor layer that includes a groove, the first diffusion section is at or in a vicinity of a bottom of the groove;
• a second diffusion section at an upper end of the groove in the semiconductor layer;
• a channel section between the first diffusion section and the second diffusion section in the semiconductor layer;
• a gate section in the groove at a position opposite to the channel section, wherein the position of the gate section is at a lower end of the groove than the upper end of the groove;
• a first electrode section on a rear surface side of the semiconductor layer, wherein the first electrode section is electrically coupled to the first diffusion section;
• a second electrode section on a top surface side of the semiconductor layer, wherein the second electrode section is electrically coupled to the second diffusion section;
• a third electrode section on the top surface side of the semiconductor layer, wherein the third electrode section is electrically coupled to the gate section;
• and
• a stress application section configured to apply one of compressive stress or tensile stress to the channel section in a normal direction to the semiconductor layer,
• wherein the first diffusion section, the second diffusion section, and the channel section constitute a p-type transistor, and
• wherein the channel section is on a {110} plane, and includes a channel orientation of <110>.

A method of manufacturing a semiconductor device, the method comprising:

• forming, in a semiconductor layer having a groove, a first diffusion section through the groove and forming a second diffusion section, thereby forming a channel section between the first diffusion section and second diffusion section, the first diffusion section being formed at a bottom of the groove, and the second diffusion section being formed at an upper end of the groove;
• forming a gate insulating film on an entire surface including an inner surface of the groove, followed by forming a gate section and removing a part protruding from the groove of the gate insulating film, the gate insulating film being made of a high-k material having a higher relative dielectric constant than a relative dielectric constant of a silicon oxide, and the gate section being made of a metal material and formed at a position opposing the channel section in the groove;
• forming a stress application section, the stress application section being configured to apply one of compressive stress and tensile stress to the channel section in a normal direction to the semiconductor layer;
• and
• forming a first electrode section, a second electrode section, and a third electrode section, the first electrode section being provided on rear surface side of the semiconductor layer and being electrically coupled to the first diffusion section, the second electrode section being provided on top surface side of the semiconductor layer and being electrically coupled to the second diffusion section, and the third electrode section being provided on the top surface side of the semiconductor layer and being electrically coupled to the gate section.

A semiconductor device, comprising:

• a semiconductor layer comprising a groove;
• a first diffusion section in the semiconductor layer, wherein the first diffusion section is at or in a vicinity of a bottom of the groove;
• a second diffusion section at an upper end of the groove in the semiconductor layer;
• a channel section between the first diffusion section and the second diffusion section in the semiconductor layer;
• a gate section in the groove at a position opposite to the channel section, wherein the position of the gate section is at a lower end of the groove than the upper end of the groove;
• a first electrode section on rear surface side of the semiconductor layer, wherein the first electrode section is electrically coupled to the first diffusion section;
• a second electrode section on a top surface side of the semiconductor layer, wherein the second electrode section is electrically coupled to the second diffusion section;
• a third electrode section on the top surface side of the semiconductor layer, wherein the third electrode section is electrically coupled to the gate section;
• a stress application section configured to apply one of compressive stress or tensile stress to the channel section in a normal direction to the semiconductor layer;
• and
• an insulating film between the first electrode section and first diffusion section, wherein generation of a dipole and flow of a tunnel current, are based on a thickness of the insulating film.

A semiconductor device, comprising:

• a semiconductor layer comprising a groove;
• a first diffusion section in the semiconductor layer, wherein the first diffusion section is at or in a vicinity of a bottom of the groove;
• a second diffusion section at an upper end of the groove in the semiconductor layer;
• a channel section between the first diffusion section and the second diffusion section in the semiconductor layer;
• a gate section in the groove at a position opposite to the channel section, wherein the position of the gate section is at a lower end of the groove than the upper end of the groove;
• a first electrode section on a rear surface side of the semiconductor layer, wherein the first electrode section is electrically coupled to the first diffusion section;
• a second electrode section on a top surface side of the semiconductor layer, wherein the second electrode section is electrically coupled to the second diffusion section;
• a third electrode section on the top surface side of the semiconductor layer, wherein the third electrode section is electrically coupled to the gate section;
• and
• a stress application section configured to apply one of compressive stress or tensile stress to the channel section in a normal direction to the semiconductor layer,
• wherein the first diffusion section, the second diffusion section, and the channel section constitute a p-type transistor, and
• wherein the channel section is on a {110} plane, and includes a channel orientation of <100>.

A semiconductor device, comprising:

• a semiconductor layer comprising a groove;
• a first diffusion section in the semiconductor layer, wherein the first diffusion section is at or in a vicinity of a bottom of the groove;
• a second diffusion section at an upper end of the groove in the semiconductor layer;
• a channel section between the first diffusion section and the second diffusion section in the semiconductor layer;
• a gate section in the groove at a position opposite to the channel section, wherein the position of the gate section is at a lower end of the groove than the upper end of the groove;
• a first electrode section on a rear surface side of the semiconductor layer, wherein the first electrode section is electrically coupled to the first diffusion section;
• a second electrode section on a top surface side of the semiconductor layer, wherein the second electrode section is electrically coupled to the second diffusion section;
• a third electrode section on the top surface side of the semiconductor layer, wherein the third electrode section is electrically coupled to the gate section;
• and
• a stress application section configured to apply one of compressive stress or tensile stress to the channel section in a normal direction to the semiconductor layer,
• wherein the first diffusion section, the second diffusion section, and the channel section constitute a n-type transistor, and
• wherein the channel section is on a {100} plane, and includes a channel orientation of <110>.